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2007 7th International Conference on ASIC最新文献

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An application specific matrix processor for signal subspace based speech enhancement in noise robust speech recognition applications 在噪声鲁棒语音识别应用中，基于信号子空间的语音增强的专用矩阵处理器
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415743
K. Natarajan, S. Arun, K. Murugaraj, M. John
{"title":"An application specific matrix processor for signal subspace based speech enhancement in noise robust speech recognition applications","authors":"K. Natarajan, S. Arun, K. Murugaraj, M. John","doi":"10.1109/ICASIC.2007.4415743","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415743","url":null,"abstract":"This work proposes the implementation of an energy efficient application specific matrix processor for speech enhancement in noisy speech recognition applications. This implementation considers speech enhancement through signal subspace based speech enhancement algorithm based on Frobenius norm constrained Singular Value Decomposition. The Singular Value Decomposition unit is used in time multiplexed fashion to perform noise reduction during feature extraction stage and it is also used for matrix inversion of the block diagonal covariance matrices for the final speech recognition block. This processor along with a 4 state Continuous Hidden Markov Model based hardware speech recognizer achieves a recognition performance improvement of 5% in noisy environments. Word samples from AN4 database is used to test the speech recognizer which has got a recognition accuracy of 96.8%. The FPGA prototyping of the above noise enhancement algorithm using the ASIP accelerator was carried out in Altera FPGA with NIOS processor.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130390465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design space exploration in multi-objective hierarchical SOC design 多目标分层SOC设计中的设计空间探索
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415581
Muhua Han, Yufeng Xie, Leibo Liu, Shaojun Wei
{"title":"Design space exploration in multi-objective hierarchical SOC design","authors":"Muhua Han, Yufeng Xie, Leibo Liu, Shaojun Wei","doi":"10.1109/ICASIC.2007.4415581","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415581","url":null,"abstract":"Nowadays, multi-objective hierarchical design methodology has received more attention for its applicability to deal with complex SOC design. Reducing decision data across hierarchy levels is crucial to the hierarchical designs. However, previous works overlooked the importance of this feature and just nested the optimizing procedures of multiple levels. This paper discussed the way to compress decision data across hierarchical levels. Pareto-optimal theory was employed and developed to explore the design space of multi-objective hierarchical system. Furthermore, this paper proved that, under the independence condition, optimization in each hierarchical level could be performed independently. This is the very first time to explore the design space of multi-objective hierarchical system formally, which contributes to the promotion of novel hierarchical partition and synthesis methodology.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124738173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Programmable Spread Spectrum Clock Generation 一个可编程扩频时钟发生器
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415635
J. Zheng, P. Ren, C. C. Shao, Yi Yang, Juncheng Wang, Wei Li, Chinglong Lin, Yuhua Cheng, Yangyuan Wang
{"title":"A Programmable Spread Spectrum Clock Generation","authors":"J. Zheng, P. Ren, C. C. Shao, Yi Yang, Juncheng Wang, Wei Li, Chinglong Lin, Yuhua Cheng, Yangyuan Wang","doi":"10.1109/ICASIC.2007.4415635","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415635","url":null,"abstract":"In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. The proposed SSCG with a third-order sigma-delta modulator can generate clocks with center spread ratios of 0.25%, 1%, 1.75%, 2.5%, 3.5%, 5% and down spread ratios of 0.5%, 2%, 3.5%, 5%, 7%, 10%. The SSCG is implemented on a chip using SMIC 0.13 um CMOS process. Measurements show that 11.31 dB attenuation of the EMI at 80 MHz with down spread ratio of 10% and 12.98 dB attenuation at 133.3 M with center spread ratio of 5% can be achieved which have a good agreement with the theoretical calculations.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125281465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Automated design method for parameters optimization of CMOS analog circuits based on adaptive genetic algorithm 基于自适应遗传算法的CMOS模拟电路参数优化自动化设计方法
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415854
Jianhai Yu, Zhigang Mao
{"title":"Automated design method for parameters optimization of CMOS analog circuits based on adaptive genetic algorithm","authors":"Jianhai Yu, Zhigang Mao","doi":"10.1109/ICASIC.2007.4415854","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415854","url":null,"abstract":"A new method for optimizing the parameters of CMOS analog circuits based on adaptive EGA (elitist genetic algorithm) is proposed in this paper. In the method the Hspice simulation tool is called to evaluate the fitness of every circuit repeatedly in a generation. According to the results of the evaluation better circuits can be reserved. By adjusting the parameters of transistors through EGA the evolution can find the circuit which will satisfy our specifications. The outcome of the experiment for a two-stage operational amplifier shows that this is an accurate and promising way in determining the device sizes in an analog circuit.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134223830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
SOC design challenges for embedded systems 嵌入式系统的SOC设计挑战
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415556
T. Hattori
{"title":"SOC design challenges for embedded systems","authors":"T. Hattori","doi":"10.1109/ICASIC.2007.4415556","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415556","url":null,"abstract":"Nowadays, LSIs can integrates billions of transistors on a chip. This means that a system or systems can be implemented in a LSI. Therefore in order to support new requirements of SOC (System on Chip) the LSI design methodology is required to be changed. SOC's are used inside embedded systems. In SOC design, it is required to achieve (1) system level optimization (2) application specific solution (3) reduction of LSI design cost (4) reduction of embedded software design cost. Platform approaches are proposed to solve these problems, but the lack of the flexibility in a platform is the most critical problem to use in the practical design. We proposed EXREAL Platform, which is the mother platform to generate application specific platforms. We are proposing the heterogeneous multi-core is better than the software solution on the standardized hardware platform. In order to achieve EXREAL Platform, we are developing three fundamental technologies that is (1) hardware interconnect technology (2) software interconnect technology (3) evaluation/validation technology. In this paper, the key concepts of EXREAL platform and some practical examples to achieve system level optimization are described.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"60 38","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134224805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PAFESD: Process algebras for electronic system designs 电子系统设计的过程代数
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415579
K. L. Man
{"title":"PAFESD: Process algebras for electronic system designs","authors":"K. L. Man","doi":"10.1109/ICASIC.2007.4415579","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415579","url":null,"abstract":"In this paper, we review a number of process algebra based formalisms that can be used for the formal specification of electronic system designs. It should be of interest to architects, engineers and researchers from the electronic design community. This paper also covers various formal techniques (process algebra based) for analysis of electronic system designs. Furthermore, we devote some space in this paper to an brief introduction of two process algebraic theories/frameworks SystemCFL and PAFSV that can be regarded as the formal languages of SystemC and SystemVerilog respectively.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134103093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Contribution to the Discrete Z-Domain Analysis of ADPLL ADPLL离散z域分析的贡献
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415598
Xin Chen, Jun Yang, Xiaoying Deng
{"title":"A Contribution to the Discrete Z-Domain Analysis of ADPLL","authors":"Xin Chen, Jun Yang, Xiaoying Deng","doi":"10.1109/ICASIC.2007.4415598","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415598","url":null,"abstract":"In this paper, a new z-domain model for all-digital phase-locked loop (ADPLL) whose output frequency is inversely proportional to the control word of digital controlled oscillator (DCO) is proposed. With this new z-domain model, bandwidth and phase margin can still be acquired for these ADPLLs. Finally, a cycle-domain simulator is written to verify the correctness of z-domain model and the results are in good agreement within only 0.3-db measurement error bars.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"96 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134476233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new soft IP core for online-testing and fault-tolerant structures 一种用于在线测试和容错结构的新型软IP核
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415803
Wang Wei, Jianhui Jiang
{"title":"A new soft IP core for online-testing and fault-tolerant structures","authors":"Wang Wei, Jianhui Jiang","doi":"10.1109/ICASIC.2007.4415803","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415803","url":null,"abstract":"This paper presents a new soft IP core to construct online-testing and fault-tolerant structures, designs some example structures with commonly-used combinational circuits as CUTs, and analyzes the performance of these CL-ACL examples from an industrial perspective, such as area cost, power consumption, and timing. The results show that CL-ACL can be used to balance the area cost and reliability among all online-testing and fault-tolerant structures, but its power consumption is rather high, the timing of CL-ACL structure is determined by CUT and must be set separately according to different CUTs.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134646057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and analysis of high power supply rejection CMOS bandgap voltage reference 高电源抑制CMOS带隙基准电压的设计与分析
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415684
Weng Qiang, Yunzhu Zhang, Jianhui Wu, Zhang Meng
{"title":"Design and analysis of high power supply rejection CMOS bandgap voltage reference","authors":"Weng Qiang, Yunzhu Zhang, Jianhui Wu, Zhang Meng","doi":"10.1109/ICASIC.2007.4415684","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415684","url":null,"abstract":"In this paper, a high power supply rejection (PSR) CMOS bandgap circuit applied in RF receiver is presented. A precise and simple PSR model, useful for pencil and paper analysis is hereby developed for the circuit. By analyzing the model, the ways to improve the circuit's performance of PSR in both low and high frequency domain are presented. The PSR of the circuit can reach 102 dB at low frequency and is more than 50 dB at high frequency. The proposed CMOS bandgap voltage reference has been implemented in Chartered 0.25-mum N-Well CMOS process.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133248339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ordered single chain tree a new coding scheme for standard cell placement 有序单链树是一种新的标准单元格放置编码方案
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415820
Kang Li, Changjiu Li, L. Tang, Juebang Yu, Yongbin Yu
{"title":"Ordered single chain tree a new coding scheme for standard cell placement","authors":"Kang Li, Changjiu Li, L. Tang, Juebang Yu, Yongbin Yu","doi":"10.1109/ICASIC.2007.4415820","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415820","url":null,"abstract":"VLSI standard cell placement is a NP hard problem, which divides into global placement and detail placement phases. In this paper, we proposed a novel coding scheme named ordered single chain tree (OSCT) for detail placement in standard cell placement. Its solution space is n!2n-1 and code length is lgn+(n-1) (where n is the number of cells), which are smaller and shorter than normalized polish expression[3] for standard cell placement. Because of its string structure, OSCT coding scheme can be employed combining with any artificial intelligent algorithms such as simulated annealing (SA) and genetic algorithm (GA) to search for optimal solution in detail placement stage conveniently. This characteristic will enhance the management scale in detail placement, release the workload and uncertainty in global placement, and thus improve whole quality of standard cell placement. Experiments on modified MCNC benchmarks show the effectiveness and efficiency of OSCT coding scheme.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133214976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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