{"title":"ADPLL离散z域分析的贡献","authors":"Xin Chen, Jun Yang, Xiaoying Deng","doi":"10.1109/ICASIC.2007.4415598","DOIUrl":null,"url":null,"abstract":"In this paper, a new z-domain model for all-digital phase-locked loop (ADPLL) whose output frequency is inversely proportional to the control word of digital controlled oscillator (DCO) is proposed. With this new z-domain model, bandwidth and phase margin can still be acquired for these ADPLLs. Finally, a cycle-domain simulator is written to verify the correctness of z-domain model and the results are in good agreement within only 0.3-db measurement error bars.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"96 10","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A Contribution to the Discrete Z-Domain Analysis of ADPLL\",\"authors\":\"Xin Chen, Jun Yang, Xiaoying Deng\",\"doi\":\"10.1109/ICASIC.2007.4415598\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a new z-domain model for all-digital phase-locked loop (ADPLL) whose output frequency is inversely proportional to the control word of digital controlled oscillator (DCO) is proposed. With this new z-domain model, bandwidth and phase margin can still be acquired for these ADPLLs. Finally, a cycle-domain simulator is written to verify the correctness of z-domain model and the results are in good agreement within only 0.3-db measurement error bars.\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"96 10\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415598\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415598","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Contribution to the Discrete Z-Domain Analysis of ADPLL
In this paper, a new z-domain model for all-digital phase-locked loop (ADPLL) whose output frequency is inversely proportional to the control word of digital controlled oscillator (DCO) is proposed. With this new z-domain model, bandwidth and phase margin can still be acquired for these ADPLLs. Finally, a cycle-domain simulator is written to verify the correctness of z-domain model and the results are in good agreement within only 0.3-db measurement error bars.