带CMOS电流模式四元加法器的6位RSD模拟-四元转换器

2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI:10.1109/ICASIC.2007.4415623

C. Chan, C. Chan, C. Choy, K. Pun

{"title":"带CMOS电流模式四元加法器的6位RSD模拟-四元转换器","authors":"C. Chan, C. Chan, C. Choy, K. Pun","doi":"10.1109/ICASIC.2007.4415623","DOIUrl":null,"url":null,"abstract":"This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDR SFDR and THD of 65.17 dB, 73.89d B and -73.26 dB at 2.5V supply voltage and 50 MHz sampling rate.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders\",\"authors\":\"C. Chan, C. Chan, C. Choy, K. Pun\",\"doi\":\"10.1109/ICASIC.2007.4415623\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDR SFDR and THD of 65.17 dB, 73.89d B and -73.26 dB at 2.5V supply voltage and 50 MHz sampling rate.\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415623\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415623","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文提出了一种采用0.35 μ m CMOS工艺的6位模数-四元转换器(AQC)。本文提出的CMOS AQC采用流水线结构，并采用冗余符号数(RSD)纠错算法。提出了一种CMOS四进制加法器来处理校正算法中的四进制加法。该变换器在2.5V电源电压和50 MHz采样率下的SNDR、SFDR和THD分别为65.17 dB、73.89 dB和-73.26 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders

This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDR SFDR and THD of 65.17 dB, 73.89d B and -73.26 dB at 2.5V supply voltage and 50 MHz sampling rate.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2007 7th International Conference on ASIC

自引率

0.00%

发文量