IET Circuits Devices Syst.最新文献_第3页

Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm 基于CORDIC算法的三角窗滑动DFT改进VLSI架构

IET Circuits Devices Syst. Pub Date : 2019-03-01 DOI: 10.1049/iet-cds.2018.5110

Tanmai Kulshreshtha, A. Dhar

引用次数: 1

Drain current modelling of double gate-all-around (DGAA) MOSFETs 双栅全能(DGAA) mosfet漏极电流建模

IET Circuits Devices Syst. Pub Date : 2019-02-04 DOI: 10.1049/IET-CDS.2018.5201

Arun Kumar, S. Bhushan, P. Tiwari

引用次数: 11

Integrated routing scheme and inverter switch to develop a mobile controlled energy saving system 综合路由方案和逆变开关，开发了移动可控节能系统

IET Circuits Devices Syst. Pub Date : 2019-01-17 DOI: 10.1049/iet-cds.2018.0086

J. Chen

{"title":"Integrated routing scheme and inverter switch to develop a mobile controlled energy saving system","authors":"J. Chen","doi":"10.1049/iet-cds.2018.0086","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.0086","url":null,"abstract":"The solutions of inverter switch and routing scheme are integrated to develop a mobile controlled energy saving system (MCESS). For the transient response problem of an n-channel metal-oxide-semiconductor field-effect transistor acting as an invert switch, and a routing scheme is solved for developing the MCESS. It can be claimed that all the mentioned previously schemes are very challenge for addressing the problems in the design of an analogue processing circuit and the implementation of Android applications (or Apps). The developed MCESS is experimentally verified automatically switch for adjusting the energy output appropriately. A control system with a solution of MCESS can replace the traditional sustainable energy systems, and obtain much longer lifetime and a steady state of the storage equipment. Furthermore, the proposed MCESS integrates Apps developed on a smart device using the Android platform with different wireless protocols, such as WiFi, Bluetooth for controlling the system with contactless. Moreover, there much experience in the development of MCESS is provided audiences with useful materials, for example a routing solution that employs wireless local area network with the WiFi protocol is implemented to transmit packets of the regulator circuit and the instant feedback display.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120264128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Programmable CCCII: reliability analysis and design methodology 可编程CCCII:可靠性分析和设计方法

IET Circuits Devices Syst. Pub Date : 2019-01-17 DOI: 10.1049/IET-CDS.2018.5165

M. K. Tiwari, N. Pandey, S. K. Paul, Saiyid Mohammad Irshad Rizvi

{"title":"Programmable CCCII: reliability analysis and design methodology","authors":"M. K. Tiwari, N. Pandey, S. K. Paul, Saiyid Mohammad Irshad Rizvi","doi":"10.1049/IET-CDS.2018.5165","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5165","url":null,"abstract":"In this study, an effective and efficient approach for reliability analysis is developed to bridge the gap between device-level reliability and that at the product level. Continual reduction of device dimensions, gate-oxide and increase in channel doping results in an increased electric field which is introducing most of the reliability concerns. Four most important reliability issues impacting circuit design are hot carrier injection, bias temperature instability, time-dependent dielectric breakdown and self-heating. As the second-generation current controlled conveyor (CCCII) circuit are used to implement oscillator, filter clock and so on, which are working continuously even in sleep mode. So it is important to take care of all the reliability aspects while designing CCCII. There is a challenge in complex design to identify which devices (MOS, resistor and capacitor) are susceptible to degradation and then redesign and mitigate this effect for a robust and reliable design. The objective of this work is to detect reliability issues and design a programmable current conveyor which can work safely for a long duration. The circuit has been designed and simulated using 28 nm CMOS technology model parameters on Cadence Virtuoso/AMS environment (ELDO simulator) using ± 1.8 V supply voltage and results have been verified with post-layout netlist.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118583239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Hardware implementation of the quasi-maximum likelihood estimator core for polynomial phase signals 多项式相位信号拟极大似然估计器核心的硬件实现

IET Circuits Devices Syst. Pub Date : 2018-12-03 DOI: 10.1049/iet-cds.2018.5112

Nevena R. Brnovic, I. Djurović, Veselin N. Ivanović, M. Simeunović

引用次数: 6

Highly-digital voltage scalable 4-bit flash ADC 高数字电压可扩展的4位闪存ADC

IET Circuits Devices Syst. Pub Date : 2018-11-26 DOI: 10.1049/iet-cds.2018.5148

Ashima Gupta, Anil Singh, A. Agarwal

引用次数: 12

Synthesis of passive fractional-order LC n-port with three element orders 三元阶无源分数阶LC n-端口的合成

IET Circuits Devices Syst. Pub Date : 2018-08-30 DOI: 10.1049/iet-cds.2018.5166

Guishu Liang, Zheng Qi

引用次数: 5

0.65 V integrable electronic realisation of integer- and fractional-order Hindmarsh-Rose neuron model using companding technique 基于扩展技术的整数阶和分数阶Hindmarsh-Rose神经元模型的0.65 V可积电子实现

IET Circuits Devices Syst. Pub Date : 2018-08-13 DOI: 10.1049/iet-cds.2018.5033

F. A. Khanday, Mohammad Rafiq Dar, N. A. Kant, J. Rosselló, C. Psychalinos

{"title":"0.65 V integrable electronic realisation of integer- and fractional-order Hindmarsh-Rose neuron model using companding technique","authors":"F. A. Khanday, Mohammad Rafiq Dar, N. A. Kant, J. Rosselló, C. Psychalinos","doi":"10.1049/iet-cds.2018.5033","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.5033","url":null,"abstract":"Some neurons like neocortical pyramidal neurons adapt with multiple time-scales, which is consistent with fractional-order differentiation. The fractional-order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer-order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer- and fractional-order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low-voltage and low-power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal-oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional-order and integer-order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118112797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

DC modelling of SOI four-gate transistor (G4FET) for implementation in circuit simulator using multivariate regression polynomial 利用多元回归多项式实现SOI四栅极晶体管(G4FET)的直流建模

IET Circuits Devices Syst. Pub Date : 2018-06-26 DOI: 10.1049/iet-cds.2018.0059

Md. Sakib Hasan, S. Islam

引用次数: 4

Two-stage current-reused variable-gain low-noise amplifier for X-band receivers in 65 nm complementary metal oxide semiconductor technology 用于65纳米互补金属氧化物半导体技术的x波段接收器的两级电流复用变增益低噪声放大器

IET Circuits Devices Syst. Pub Date : 2018-06-15 DOI: 10.1049/iet-cds.2017.0538

Mohammad Reza Nikbakhsh, E. Abiri, Hossein Ghasemian, M. Salehi

{"title":"Two-stage current-reused variable-gain low-noise amplifier for X-band receivers in 65 nm complementary metal oxide semiconductor technology","authors":"Mohammad Reza Nikbakhsh, E. Abiri, Hossein Ghasemian, M. Salehi","doi":"10.1049/iet-cds.2017.0538","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0538","url":null,"abstract":"In this study, a variable gain low noise amplifier (VG-LNA) working at X band is designed and simulated in 65 nm complementary metal oxide semiconductor technology. A two-stage structure is used in the proposed VG-LNA. Besides, the current-reused technique causes a higher gain without consuming extra power. As an on-chip voltage (\u0000 V cnt\u0000) is changed, the gain continuously and almost linearly varies. The highest gain is 27.8 dB that can be reduced to 8.3 dB almost linearly and continuously as the control voltage is increased. The lowest value of S11 is −28.2 dB at 10 GHz. Also, NF is <2.75 dB at the operating frequency range; while NF\u0000 min\u0000 = 1.8 dB. The highest value of third-order intercept point is 2.03 dBm that always remain larger than −10.1 dBm. The basic advantage of this structure in comparison with other similar works is that not only the key parameters remain fixed with reduction of gain, but also the operation range of V cnt\u0000 is widened from 0.3 V to V dd\u0000 in order to extend the gain control range to 19.5 dB. Moreover, these results are achieved in a situation that the proposed VG-LNA draws only 3.9 mA from a 1.2 V.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117845898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8