IET Circuits Devices Syst.最新文献_第2页

Feasibility study of the feed-forward carrier recovery technique for E-band integrated receivers e波段集成接收机前馈载波恢复技术的可行性研究

IET Circuits Devices Syst. Pub Date : 2019-08-07 DOI: 10.1049/IET-CDS.2019.0063

A. Dyskin, I. Kallfass

引用次数: 2

Optical MEMS accelerometer sensor relying on a micro-ring resonator and an elliptical disk 基于微环谐振器和椭圆盘的光学MEMS加速度计传感器

IET Circuits Devices Syst. Pub Date : 2019-07-12 DOI: 10.1049/IET-CDS.2019.0029

Ali Kazemi Nasaban Shotorban, Kian Jafari, K. Abedi

引用次数: 13

Approximate computing using frequency upscaling 近似计算使用频率升级

IET Circuits Devices Syst. Pub Date : 2019-06-10 DOI: 10.1049/IET-CDS.2018.5422

Junqi Huang, T. Kumar, Haider Abbas, F. Lombardi

{"title":"Approximate computing using frequency upscaling","authors":"Junqi Huang, T. Kumar, Haider Abbas, F. Lombardi","doi":"10.1049/IET-CDS.2018.5422","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5422","url":null,"abstract":"This study presents frequency upscaling as a technique for developing error resilient arithmetic designs in approximate computing whereby the input signal frequency of the circuit is upscaled beyond its largest operating value in generating errors in the arithmetic operation while speeding up the computational throughput. This study initially presents the mathematical modelling of frequency upscaling for both exact and inexact full adders. An exhaustive simulation and evaluation of 4 and 8 bits subtraction followed by addition of two images and approximate discrete cosine transform (DCT) is pursued using exact and inexact circuits when subjected to the proposed technique. The results estimated using the proposed model show good agreement with the simulation results. The normalised mean error distance of subtraction using an inexact circuit is close to the exact value for different technology nodes. The peak signal-to-noise ratio (PSNR) results for the addition of two images show that the inexact full adder achieves a higher output image quality than the exact circuit when the frequency is scaled up. Also, in an approximate DCT, the input frequency of an inexact full adder can be scaled up significantly higher than an exact full adder without a significant decrease in PSNR value.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117962316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Observation of robust chaos in 3D electronic system 三维电子系统鲁棒混沌的观察

IET Circuits Devices Syst. Pub Date : 2019-05-20 DOI: 10.1049/IET-CDS.2018.5544

Soumyajit Seth

引用次数: 3

Mathematical model for the analysis of series-parallel compensated wireless power transfer system for different misalignments 串并联补偿无线电力传输系统在不同不对准情况下的数学模型分析

IET Circuits Devices Syst. Pub Date : 2019-05-13 DOI: 10.1049/IET-CDS.2018.5044

B. Kushwaha, Gautam Rituraj, Praveen Kumar, P. Bauer

引用次数: 6

Hardware architectures for PRESENT block cipher and their FPGA implementations 分组密码的硬件体系结构及其FPGA实现

IET Circuits Devices Syst. Pub Date : 2019-05-13 DOI: 10.1049/IET-CDS.2018.5273

J. Pandey, Tarun Goel, A. Karmakar

引用次数: 11

All-digital delay line-based time difference amplifier in 65 nm CMOS technology 基于65纳米CMOS技术的全数字延迟线时差放大器

IET Circuits Devices Syst. Pub Date : 2019-04-30 DOI: 10.1049/IET-CDS.2018.5304

Ramin Razmdideh, M. Saneei

引用次数: 0

Novel adaptive blind calibration technique of time-skew mismatches for any channel time-interleaved analogue-to-digital converters 针对任意信道时交错模数转换器时偏失匹配的自适应盲校正技术

IET Circuits Devices Syst. Pub Date : 2019-04-18 DOI: 10.1049/IET-CDS.2018.5560

Yongtao Qiu, Jie Zhou, Youjiang Liu, Guifu Zhang, Yinong Liu

引用次数: 2

Rapid calibration of bits weights error for high-resolution successive approximation register ADC 高分辨率逐次逼近寄存器ADC位权误差的快速校正

IET Circuits Devices Syst. Pub Date : 2019-04-15 DOI: 10.1049/IET-CDS.2018.5220

Lu Liu, Daiguo Xu, Shiliu Xu

{"title":"Rapid calibration of bits weights error for high-resolution successive approximation register ADC","authors":"Lu Liu, Daiguo Xu, Shiliu Xu","doi":"10.1049/IET-CDS.2018.5220","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5220","url":null,"abstract":"This study presents the rapid calibration of bits weights error for an 18 bit successive approximation register analogue-to-digital converter (ADC). This calibration technique is a new hybrid algorithm. Comparing to the traditional methods, this technique significantly reduces the convergence time and improves the accuracy of bits weights error estimation. There is no wasteful time in the correction process. This proposed approach estimates the bits weights error not only from the digital-to-analogue converter capacitor mismatch, inter-stage gain error, but also the metal insulator metal (MIM), capacitor second-order voltage coefficient in the ultra-high-resolution ADC. The proposed algorithm has been verified with a test 18 bit ADC chip, where measured results show the calibration is able to improve the peak integral nonlinearity (INL), of the ADC from 29 to 1.0 LSB after calibration. Measured results also show the signal-to-noise and distortion ratio/spurious-free dynamic range of the ADC improves from 83/94 to 96/127 dB after calibration. It will be seen that the calibration is achieved in ∼4k cycles, which is more than ×25 faster than previously published algorithm.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119697012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Resource-efficient FPGA implementation of perspective transformation for bird's eye view generation using high-level synthesis framework 基于高级综合框架的鸟瞰图生成视角转换的资源高效FPGA实现

IET Circuits Devices Syst. Pub Date : 2019-03-07 DOI: 10.1049/IET-CDS.2018.5263

M. Bilal

{"title":"Resource-efficient FPGA implementation of perspective transformation for bird's eye view generation using high-level synthesis framework","authors":"M. Bilal","doi":"10.1049/IET-CDS.2018.5263","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5263","url":null,"abstract":"Bird's eye view (BEV) generation from front-looking video stream is considered an important pre-processing task in various computer vision applications such as driver assistance systems. In this work, hardware implementation of this process using high-level synthesis in Simulink environment has been considered for rapid prototyping under real-time constraints. Traditionally, researchers have employed lookup table-based approaches to circumvent the exorbitant cost of implementing arithmetic modules associated with the perspective transformation. The hardware implementation scheme proposed here, however, demonstrates that a polynomial approximation over the limited domain of the involved operands not only saves precious hardware resources but also provides better fixed-point precision. Synthesis results on Zynq-7000 FPGA show that the proposed circuit reduces the block memory utilisation by 9% compared to the lookup table-based built-in Simulink Vision HDL block. The proposed design evaluates the results in fixed-point format which is essential for subsequent bilinear interpolation to produce high-fidelity output frame, albeit at the cost of 4% increase in DSP48E utilisation. The approximation error of the proposed solution is less than quarter-pixel on average. The proposed hardware has been integrated as an IP core in a hardware-software co-design system. The whole framework is publicly available to facilitate practitioners and researchers.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120457066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4