IET Circuits Devices Syst.最新文献

A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage 具有前置放大器增强级的低偏置低功率高速动态锁存器比较器

IET Circuits Devices Syst. Pub Date : 2020-12-17 DOI: 10.1049/cds2.12008

Jérôme Folla Kamdem, M. Crespo, W. T. Evariste, M. Bhuiyan, A. Cicuttin, E. Bernard, M. Reaz

引用次数: 19

Embedding delay-based physical unclonable functions in networks-on-chip 在片上网络中嵌入基于延迟的物理不可克隆函数

IET Circuits Devices Syst. Pub Date : 2020-12-15 DOI: 10.1049/cds2.12004

Prasad Nagabhushanamgari, Vikash Sehwag, I. Chakrabarti, S. Chattopadhyay

引用次数: 1

Design of 10T SRAM cell with improved read performance and expanded write margin 10T SRAM单元的设计，提高了读取性能并扩大了写入余量

IET Circuits Devices Syst. Pub Date : 2020-12-15 DOI: 10.1049/cds2.12006

Ashish Sachdeva, V. Tomar

{"title":"Design of 10T SRAM cell with improved read performance and expanded write margin","authors":"Ashish Sachdeva, V. Tomar","doi":"10.1049/cds2.12006","DOIUrl":"https://doi.org/10.1049/cds2.12006","url":null,"abstract":"Ashish Sachdeva, ECE Department, GLA University, Mathura, India. Email: er.ashishsachdeva@gmail.com Funding Information The authors have no relevant financial or non‐ financial/ Funding interests to disclose. Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78� and 2.326� in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03� in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134629862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

On the applicability of two-bit carbon nanotube through-silicon via for power distribution networks in 3-D integrated circuits 二元碳纳米管硅通孔在三维集成电路配电网中的适用性研究

IET Circuits Devices Syst. Pub Date : 2020-12-13 DOI: 10.1049/cds2.12010

Qing-Hao Hu, Wensheng Zhao, Kai Fu, Dawei Wang, Gaofeng Wang

引用次数: 3

Analytical model and simulation-based analysis of a work function engineered triple metal tunnel field-effect transistor device showing excellent device performance 基于解析模型和仿真的三金属隧道场效应晶体管器件的功函数分析显示了优异的器件性能

IET Circuits Devices Syst. Pub Date : 2020-12-13 DOI: 10.1049/cds2.12009

R. Bose, J. Roy

{"title":"Analytical model and simulation-based analysis of a work function engineered triple metal tunnel field-effect transistor device showing excellent device performance","authors":"R. Bose, J. Roy","doi":"10.1049/cds2.12009","DOIUrl":"https://doi.org/10.1049/cds2.12009","url":null,"abstract":"In this study, the authors propose a work function engineered (WFE) triple metal (TM) tunnel field ‐ effect transistor (TFET) device, which exhibits lower subthreshold slope (SS) and better on to off current ratio in comparison with conventional double gate TFET and dual metal TFET device. An analytical model is formulated to study the performance of the proposed device. A simulation ‐ based study of these TFET devices has been carried out with the help of 2D TCAD (Technology Computer Aided Design) Sentaurus device simulator for different channel length values in order to validate our proposed mathematical model. The source side n þ pocket in the proposed triple metal (TM) TFET device enhances tunnelling probability thus increasing on current and off current is controlled by another n ‐ pocket near drain side. Significantly lower subthreshold slope (less than 10 mV/decade), high transconductance (in the order of 10 (cid:0) 4 S/μm), low energy ‐ delay product (24.601 fJ ‐ ns/μm) obtained for TM WFE TFET makes this device more suitable for digital logic and RF (Radio Frequency) application.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133828297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

All-digital built-in self-test scheme for charge-pump phase-locked loops 全数字内置自检方案的电荷泵锁相环

IET Circuits Devices Syst. Pub Date : 2020-12-10 DOI: 10.1049/cds2.12000

Lanhua Xia, Jifei Tang

引用次数: 3

Fast transient low-dropout regulator with undershoot and settling time reduction technique 快速瞬态低差调节器与欠冲和沉降时间减少技术

IET Circuits Devices Syst. Pub Date : 2019-10-10 DOI: 10.1049/IET-CDS.2019.0013

Sung-hwan Lee, I. Kwon

引用次数: 0

Ultra-low voltage, power efficient continuous-time filters in 180 nm CMOS technology 超低电压，功率高效的连续时间滤波器在180纳米CMOS技术

IET Circuits Devices Syst. Pub Date : 2019-10-01 DOI: 10.1049/IET-CDS.2018.5485

S. Rekha, V. M. Harishchandra, T. Laxminidhi

引用次数: 0

High throughput FIR filter architectures using retiming and modified CSLA based adders 使用重定时和改进的基于CSLA的加法器的高吞吐量FIR滤波器架构

IET Circuits Devices Syst. Pub Date : 2019-10-01 DOI: 10.1049/IET-CDS.2019.0130

Pramod Patali, S. Kassim

{"title":"High throughput FIR filter architectures using retiming and modified CSLA based adders","authors":"Pramod Patali, S. Kassim","doi":"10.1049/IET-CDS.2019.0130","DOIUrl":"https://doi.org/10.1049/IET-CDS.2019.0130","url":null,"abstract":"A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add–multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry-select adder (CSLA) structures are obtained by combining modified forms of carry look-ahead and carry-skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power–delay product and area–delay product of the proposed filter-2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119404380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms 基于符号技术和多目标算法的差分压控振荡器的快速优化设计

IET Circuits Devices Syst. Pub Date : 2019-08-07 DOI: 10.1049/IET-CDS.2018.5617

Madhusmita Panda, S. Patnaik, A. K. Mal, Sumalya Ghosh

{"title":"Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms","authors":"Madhusmita Panda, S. Patnaik, A. K. Mal, Sumalya Ghosh","doi":"10.1049/IET-CDS.2018.5617","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5617","url":null,"abstract":"In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118732781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8