All-digital built-in self-test scheme for charge-pump phase-locked loops

Charge ‐ pump phase ‐ locked loop (CP ‐ PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all ‐ digital built ‐ in self ‐ test structure of CP ‐ PLL especially suitable for low ‐ cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP ‐ PLL under test. It reduces the requirement of additional external test clocks and high ‐ performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.