全数字内置自检方案的电荷泵锁相环

Lanhua Xia, Jifei Tang
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引用次数: 3

摘要

电荷泵锁相环(CP - PLL)在片上系统(soc)中广泛用于产生时序信号。然而,soc中嵌入的内核数量、有限的I/O端口资源以及外部测试设备的成本导致测试复杂性和成本的增加。提出了一种全数字内建的CP - PLL自检结构,特别适用于I/O端口资源有限时的低成本生产测试。结构简单,易于实现,只需几个dff, mux和一些现有的CP - PLL电路进行测试。它减少了额外的外部测试时钟和高性能测试设备的需求,从而降低了整个集成电路的测试成本。结合所提出的定标技术,消除了压控振荡器输入电压初值不确定对故障覆盖率的影响。从而提高了试验结果的可靠性。实验结果证明了该方案的有效性,故障覆盖率高达99.16%。此外,提出了低面积开销1.37%的物理芯片设计方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
All-digital built-in self-test scheme for charge-pump phase-locked loops
Charge ‐ pump phase ‐ locked loop (CP ‐ PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all ‐ digital built ‐ in self ‐ test structure of CP ‐ PLL especially suitable for low ‐ cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP ‐ PLL under test. It reduces the requirement of additional external test clocks and high ‐ performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.
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