发布求助
文献互助 智能选刊 最新文献

IET Circuits Devices Syst.最新文献

筛选
英文 中文
Closed-form model for the open circuit voltage of solar cells with shunt resistance, bias-dependent photocurrent and double exponential terms 具有并联电阻、偏置相关光电流和双指数项的太阳能电池开路电压的封闭模型
IET Circuits Devices Syst. Pub Date : 2012-07-01 DOI: 10.1049/iet-cds.2011.0173
H. Saleem, S. Karmalkar
{"title":"Closed-form model for the open circuit voltage of solar cells with shunt resistance, bias-dependent photocurrent and double exponential terms","authors":"H. Saleem, S. Karmalkar","doi":"10.1049/iet-cds.2011.0173","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0173","url":null,"abstract":"The parasitic shunt resistance, bias dependence of the photocurrent and phenomena causing a second exponential term in the current density ( J )-voltage ( V ) equation reduce the open circuit voltage, V oc , of illuminated solar cells below the ideal value predicted by the J - V equation having only a single exponential term. This study reports an approximate closed-from solution of the transcendental V oc equation which directly reflects these losses. The solution estimates V oc as a weighted parallel combination of the limiting V oc values corresponding to the domination of one of the several terms of the V oc equation. The solution allows quick design calculation of the V oc of a wide variety of cells in terms of all physical parameters, and provides insight into the influence of losses owing to various factors.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126847005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-resolution based sensitivity analysis of complex non-linear circuits 基于多分辨率的复杂非线性电路灵敏度分析
IET Circuits Devices Syst. Pub Date : 2012-06-28 DOI: 10.1049/iet-cds.2010.0429
S. Barmada, A. Musolino, R. Rizzo, M. Tucci
{"title":"Multi-resolution based sensitivity analysis of complex non-linear circuits","authors":"S. Barmada, A. Musolino, R. Rizzo, M. Tucci","doi":"10.1049/iet-cds.2010.0429","DOIUrl":"https://doi.org/10.1049/iet-cds.2010.0429","url":null,"abstract":"This study addresses the sensitivity analysis of non-linear circuits in their transient and periodic behaviour. The circuits here considered are built of connections of N-ports with frequency-dependent parameters whose input and output quantities are expanded in the wavelet domain. The use of wavelet instead of the Fourier analysis allows a significant increase in the sparsity of the matrices with a comparable accuracy and convergence rate. In addition, by using the proper wavelet basis, it is possible to analyse both the steady state and the transient behaviour. The adjoint system method is used to obtain the sensitivities of the response of the circuit with respect to the design parameters. The multiport connection is described in terms of scattering parameters and the hierarchical approach is extended to the adjoint system. Computational aspects are discussed and examples of application of the proposed technique are reported. The results are compared with those obtained by the use of other techniques.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121986256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
High-quality factor asymmetric-slope band-pass filters: A fractional-order capacitor approach 高质量因数不对称斜率带通滤波器:分数阶电容方法
IET Circuits Devices Syst. Pub Date : 2012-06-28 DOI: 10.1049/iet-cds.2011.0239
P. Ahmadi, B. Maundy, A. Elwakil, L. Belostotski
{"title":"High-quality factor asymmetric-slope band-pass filters: A fractional-order capacitor approach","authors":"P. Ahmadi, B. Maundy, A. Elwakil, L. Belostotski","doi":"10.1049/iet-cds.2011.0239","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0239","url":null,"abstract":"This study presents new techniques for implementing continuous-time second-order band-pass filters with high-quality factors and asymmetric slopes. The techniques are centred around the realisation of two non-conventional transfer functions which include the non-integer-order Laplacian operator sα; 0<α<1. Four main possible circuit realisations; one based on a frequency-dependent negative resistor (FDNR), another based on an inductor and two based on multiple amplifier biquads (MABs) are given and verified using Spice and experimentally for both transfer functions. In addition, a field programmable analogue array (FPAA) realisation is tested and verified. Last but not least, a possible realisation using current conveyors is also given, tested and verified.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129803238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 98
On the use of Karatsuba formula to detect errors in GF((2(sup)n(/sup))(sup)2(/sup)) multipliers 利用Karatsuba公式检测GF((2(sup)n(/sup))(sup)2(/sup))乘数中的误差
IET Circuits Devices Syst. Pub Date : 2012-06-28 DOI: 10.1049/iet-cds.2011.0278
S. Pontarelli, A. Salsano
{"title":"On the use of Karatsuba formula to detect errors in GF((2(sup)n(/sup))(sup)2(/sup)) multipliers","authors":"S. Pontarelli, A. Salsano","doi":"10.1049/iet-cds.2011.0278","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0278","url":null,"abstract":"Galois fields are widely used in cryptographic applications. The detection of an error caused by a fault in a cryptographic circuit is important to avoid undesirable behaviours of the system that could be used to reveal secret information. One of the methods used to avoid these behaviours is the concurrent error detection. Multiplication in finite field is one of the most important operations and is widely used in different cryptographic systems. The authors propose in this study an error-detection method for composite finite-field multipliers based on the use of Karatsuba formula. The Karatsuba formula can be used in GF((2n)2) field to decrease the hardware complexity of the finite-field multiplier. The authors propose a novel finite-field multiplier with concurrent error-detection capabilities based on the Karatsuba formula. How the error-detection capabilities of this multiplier are able to face a wide range of fault-based attacks is also shown.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126397055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-Q metamaterial interdigital transmission line based on complementary spiral resonators for low phase noise voltage-controlled oscillator 基于互补螺旋谐振器的低相位噪声压控振荡器高q超材料数字间传输线
IET Circuits Devices Syst. Pub Date : 2012-06-28 DOI: 10.1049/iet-cds.2011.0154
J. Choi, C. Seo
{"title":"High-Q metamaterial interdigital transmission line based on complementary spiral resonators for low phase noise voltage-controlled oscillator","authors":"J. Choi, C. Seo","doi":"10.1049/iet-cds.2011.0154","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0154","url":null,"abstract":"In this study, the high-quality factor ( Q ) metamaterial interdigital transmission line (TL) based on the complementary spiral resonators (CSRs) is presented for reducing the phase noise of the voltage-controlled oscillator (VCO). The high- Q metamaterial TL is realised by adopting the array of the CSRs etched on the ground plane and the interdigital centre line on the signal plane. The interdigital centre line on the signal plane has been used to obtain higher Q value than that of the conventional implementation. The resonance properties and inherent Q value saturation of the proposed high- Q metamaterial interdigital TL have been analysed as follows: width of the centre line on the signal plane, dimensions of the CSRs, current directions between the CSRs, number of the unit cell-pair of the CSRs and whether or not there is the interdigital structure. The phase noise and tuning range of the proposed VCO are -127.50 to -124.87-dBc/Hz at 100-kHz and 5.744-5.86-GHz.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116715542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Configuration for realising a current-mode universal filter and dual-mode quadrature single resistor controlled oscillator 实现电流型通用滤波器和双模正交单电阻控制振荡器的配置
IET Circuits Devices Syst. Pub Date : 2012-06-28 DOI: 10.1049/iet-cds.2011.0160
K. K. Abdalla, D. Bhaskar, R. Senani
{"title":"Configuration for realising a current-mode universal filter and dual-mode quadrature single resistor controlled oscillator","authors":"K. K. Abdalla, D. Bhaskar, R. Senani","doi":"10.1049/iet-cds.2011.0160","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0160","url":null,"abstract":"A new universal single input multiple output (SIMO)-type universal filter configuration using three dual output current conveyors (DOCCII) and five grounded passive elements is proposed which can realise all the five basic filtering functions namely low pass, high pass, band pass, band stop and all pass in current mode from the same configuration. With appropriate modification of one connection, the circuit can also be converted into a quadrature oscillator capable of providing two voltage mode outputs and as well as two current mode outputs in quadrature. The workability of the new configuration has been demonstrated by simulation program with integrated circuit emphasis (SPICE) simulation results based on a complementary metal oxide semiconductor field effect transistor current conveyor II (CMOS CCII) implemented in 0.35-μm technology.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125807111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Subthreshold CMOS voltage reference circuit with body bias compensation for process variation 具有体偏置补偿的亚阈值CMOS电压基准电路
IET Circuits Devices Syst. Pub Date : 2012-06-28 DOI: 10.1049/iet-cds.2011.0170
Hao Luo, Yan Han, R. Cheung, G. Liang, Dazhong Zhu
{"title":"Subthreshold CMOS voltage reference circuit with body bias compensation for process variation","authors":"Hao Luo, Yan Han, R. Cheung, G. Liang, Dazhong Zhu","doi":"10.1049/iet-cds.2011.0170","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0170","url":null,"abstract":"This study presents a subthreshold complementary metal oxide semiconductor (CMOS) voltage reference circuit that adopts dynamical body bias to compensate the process-related reference voltage fluctuation. The proposed circuit generates a mean reference voltage of 0.781 V at 1.2 V supply and 27°C, reduces the standard deviation (σ) of the reference voltage from 11 mV to only 3 mV, and meanwhile improves the power supply rejection ratio from -30.7 to -51.4 dB. The average temperature coefficient measured from 0 to 100°C is 48 ppm/°C, and the line regulation is 0.34%/V in a supply voltage ranging from 1.2 to 2.3 V. The maximum supply current is 8.1 μA at 1.2 V supply and 100°C, and the chip area is 0.0533 mm 2 in 0.13-μm CMOS technology.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123606462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Non-recursive decimation filters with arbitrary integer decimation factors 具有任意整数抽取因子的非递归抽取过滤器
IET Circuits Devices Syst. Pub Date : 2012-06-28 DOI: 10.1049/iet-cds.2011.0240
K. Mondal, S. Mitra
{"title":"Non-recursive decimation filters with arbitrary integer decimation factors","authors":"K. Mondal, S. Mitra","doi":"10.1049/iet-cds.2011.0240","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0240","url":null,"abstract":"Cascaded integrator comb (CIC) filters are in wide use in oversampled analog-to-digital converters. In this study, the authors advances three new cascaded decimator structures with integer coefficients designed using a polynomial factorisation approach. Each one of the designed decimators shows better stopband attenuation for a given order and decimation factor than the CIC or recently proposed generalised comb filter (GCF) and may not require any prefilter for performance enhancement. A fourth new decimator structure is a hybrid between the CIC and GCF with coefficients approximated by integers. Decimator power dissipation analysis and optimisation have previously been done either by counting the number of additions per sample rate or by focusing on register clock distribution. The authors propose a new metric for estimating the power dissipation of a filter structure from its architecture accounting for dissipation both in the adder cells and the flip-flops. The authors show frequency domain characteristics and compare power dissipations of all the new structures using a representative example.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123693809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Non-linear coupling voltage of split-gate flash memory cells with additional top coupling gate 附加顶部耦合栅极的分栅闪存单元非线性耦合电压
IET Circuits Devices Syst. Pub Date : 2012-05-01 DOI: 10.1049/iet-cds.2011.0252
S. Saha
{"title":"Non-linear coupling voltage of split-gate flash memory cells with additional top coupling gate","authors":"S. Saha","doi":"10.1049/iet-cds.2011.0252","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0252","url":null,"abstract":"The study presents the dependence of floating gate (FG) coupling potential,\u0000 V FG \u0000on the source line (SL) programming voltage,\u0000 V SL \u0000of the split-gate flash memory cells with an additional top coupling gate above FG, called the `SG-TCG` cells. The mathematical analysis shows non-linear\u0000 V FG \u0000against\u0000 V SL \u0000behaviour of SG-TCG cells depending on the operation region of FG-MOSFETs. It is found that as the value of\u0000 V SL \u0000increases, the value of\u0000 V FG \u0000initially increases steeply, then gradually and finally, linearly with a lower slope. This anomalous\u0000 V FG \u0000against\u0000 V SL \u0000behaviour is because of the potential drop in the bulk of FG-MOSFETs by the applied\u0000 V SL \u0000. The mathematical analysis, also, shows SL coupling factor (κ\u0000 SL \u0000) roll-off because of the increase in the FG-MOSFETs body potential with the increase in\u0000 V SL \u0000. In addition, κ\u0000 SL \u0000is shown to approach a constant value in the saturation region of FG-MOSFETs where\u0000 V FG \u0000is less susceptible to supply voltage fluctuation. The mathematical analysis agrees very well with the numerical device simulation. The study, clearly, shows that in order to achieve higher shift in programme cell threshold voltage and reduce performance variability owing to supply voltage fluctuation, the target programming bias\u0000 V SL \u0000of nanoscale SG-TCG cells must be higher than the saturation voltage of FG-MOSFETs.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125546986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Low-power oscillator for passive radio frequency identification transponders 用于无源射频识别应答器的低功率振荡器
IET Circuits Devices Syst. Pub Date : 2012-04-03 DOI: 10.1049/iet-cds.2011.0279
Mahzad Azarmehr, R. Rashidzadeh, M. Ahmadi
{"title":"Low-power oscillator for passive radio frequency identification transponders","authors":"Mahzad Azarmehr, R. Rashidzadeh, M. Ahmadi","doi":"10.1049/iet-cds.2011.0279","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0279","url":null,"abstract":"Passive radio frequency identification tags extract energy from incoming electromagnetic waves to power up their internal circuitry. Such a limited source of power demands efficient circuits to minimise the power consumption. In this work a new technique is proposed to design a low-power ring oscillator in which the voltage swing of internal nodes are constrained to lower the dynamic power consumption. The proposed power reduction technique can be employed for RFID tags operating over different frequency bands from low frequency (LF) to microwave. A low-power oscillator operating in the medium-frequency range (6–16 MHz) for applications such as electronic article surveillance and item management has been implemented in this work. Post-layout simulation results using STMicroelectronics CMOS 65 nm technology indicate that the proposed method can reduce the power consumption by more than 25%.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115899952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信