{"title":"Non-linear coupling voltage of split-gate flash memory cells with additional top coupling gate","authors":"S. Saha","doi":"10.1049/iet-cds.2011.0252","DOIUrl":null,"url":null,"abstract":"The study presents the dependence of floating gate (FG) coupling potential,\n V FG \non the source line (SL) programming voltage,\n V SL \nof the split-gate flash memory cells with an additional top coupling gate above FG, called the `SG-TCG` cells. The mathematical analysis shows non-linear\n V FG \nagainst\n V SL \nbehaviour of SG-TCG cells depending on the operation region of FG-MOSFETs. It is found that as the value of\n V SL \nincreases, the value of\n V FG \ninitially increases steeply, then gradually and finally, linearly with a lower slope. This anomalous\n V FG \nagainst\n V SL \nbehaviour is because of the potential drop in the bulk of FG-MOSFETs by the applied\n V SL \n. The mathematical analysis, also, shows SL coupling factor (κ\n SL \n) roll-off because of the increase in the FG-MOSFETs body potential with the increase in\n V SL \n. In addition, κ\n SL \nis shown to approach a constant value in the saturation region of FG-MOSFETs where\n V FG \nis less susceptible to supply voltage fluctuation. The mathematical analysis agrees very well with the numerical device simulation. The study, clearly, shows that in order to achieve higher shift in programme cell threshold voltage and reduce performance variability owing to supply voltage fluctuation, the target programming bias\n V SL \nof nanoscale SG-TCG cells must be higher than the saturation voltage of FG-MOSFETs.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Circuits Devices Syst.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/iet-cds.2011.0252","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
The study presents the dependence of floating gate (FG) coupling potential,
V FG
on the source line (SL) programming voltage,
V SL
of the split-gate flash memory cells with an additional top coupling gate above FG, called the `SG-TCG` cells. The mathematical analysis shows non-linear
V FG
against
V SL
behaviour of SG-TCG cells depending on the operation region of FG-MOSFETs. It is found that as the value of
V SL
increases, the value of
V FG
initially increases steeply, then gradually and finally, linearly with a lower slope. This anomalous
V FG
against
V SL
behaviour is because of the potential drop in the bulk of FG-MOSFETs by the applied
V SL
. The mathematical analysis, also, shows SL coupling factor (κ
SL
) roll-off because of the increase in the FG-MOSFETs body potential with the increase in
V SL
. In addition, κ
SL
is shown to approach a constant value in the saturation region of FG-MOSFETs where
V FG
is less susceptible to supply voltage fluctuation. The mathematical analysis agrees very well with the numerical device simulation. The study, clearly, shows that in order to achieve higher shift in programme cell threshold voltage and reduce performance variability owing to supply voltage fluctuation, the target programming bias
V SL
of nanoscale SG-TCG cells must be higher than the saturation voltage of FG-MOSFETs.