使用重定时和改进的基于CSLA的加法器的高吞吐量FIR滤波器架构

Pramod Patali, S. Kassim
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引用次数: 25

摘要

本文提出了一种通过有效地使用重定时和有效的加乘运算来提高FIR滤波器吞吐量的方法。通过将进位预读加法器和进位跳加法器概念的改进形式结合到连接的CSLA模块中,获得了延迟、节能和面积高效的线性和平方根进位选择加法器(CSLA)结构。通过模块携带子生成块快速生成和传输终端模块携带子,提高了计算速度。利用所提出的平方根CSLA进行部分乘积加法,提高了布斯乘法器的延迟性能。所提出的滤波器的两个版本是(a)高吞吐量低功耗和低复杂的重定时FIR滤波器和(b)高吞吐量节能重定时FIR滤波器。对于长度为64的改进型转置滤波器,该滤波器的关键路径延迟、功率、功率延迟积和面积延迟积分别比柔性重定时滤波器降低了71%、382%、82%和78%,比改进型转置滤波器分别降低了40%、111%、47%和37%。采用带有gpdk 45 nm标准单元库的Cadence软件进行设计和实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High throughput FIR filter architectures using retiming and modified CSLA based adders
A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add–multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry-select adder (CSLA) structures are obtained by combining modified forms of carry look-ahead and carry-skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power–delay product and area–delay product of the proposed filter-2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.
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