基于符号技术和多目标算法的差分压控振荡器的快速优化设计

Madhusmita Panda, S. Patnaik, A. K. Mal, Sumalya Ghosh
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引用次数: 8

摘要

在这项工作中,为基于4位,10 MHz VCO的ADC设计了一个DVCO。采用基于分层行列式展开的DDD技术对所设计的DVCO进行了噪声建模和分析。用这些方法得到的结果与SPICE的结果几乎相同。然而,计算时间从使用数值方法(SPICE)的13.7秒减少到使用DDD技术的4.5秒。然后使用多目标优化技术(如IDEA和MOPSO)对设计的DVCO进行优化,以提高性能。在理想的振荡频率下,低功耗和低相位噪声是优化的目标。对于这种设计的DVCO, IDEA优化方法似乎比MOPSO更有效。然后使用SPICE在不同的工艺角模拟优化后的DVCO。所设计的DVCO在1 MHz偏移时的相位噪声从- 80.3 dBc/Hz改善到- 88.9 dBc/Hz。功耗也从38.4 mw降低到34.5 mw,实现了3.49 GHz的目标频率。DVCO性能的这些改进使设计的ADC的ENOB从3.6位提高到4.2位。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms
In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.
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