高分辨率逐次逼近寄存器ADC位权误差的快速校正

Lu Liu, Daiguo Xu, Shiliu Xu
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引用次数: 4

摘要

本研究提出了一个18位连续逼近寄存器模数转换器(ADC)的位权重误差的快速校准方法。该标定技术是一种新的混合算法。与传统方法相比,该方法显著缩短了收敛时间,提高了码权误差估计的精度。在校正过程中不会浪费时间。该方法不仅可以从数模转换器电容失配、级间增益误差,还可以从超高分辨率ADC的金属绝缘体(MIM)、电容二阶电压系数等方面估计位权误差。该算法已在一个18位ADC测试芯片上得到验证,测量结果表明,校正后的ADC的峰值积分非线性(INL)从29提高到1.0 LSB。测量结果还表明,校正后的ADC的信噪比和失真比/无杂散动态范围从83/94提高到96/127 dB。可以看到,校准在~ 4k周期内实现,比以前发表的算法快×25多。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Rapid calibration of bits weights error for high-resolution successive approximation register ADC
This study presents the rapid calibration of bits weights error for an 18 bit successive approximation register analogue-to-digital converter (ADC). This calibration technique is a new hybrid algorithm. Comparing to the traditional methods, this technique significantly reduces the convergence time and improves the accuracy of bits weights error estimation. There is no wasteful time in the correction process. This proposed approach estimates the bits weights error not only from the digital-to-analogue converter capacitor mismatch, inter-stage gain error, but also the metal insulator metal (MIM), capacitor second-order voltage coefficient in the ultra-high-resolution ADC. The proposed algorithm has been verified with a test 18 bit ADC chip, where measured results show the calibration is able to improve the peak integral nonlinearity (INL), of the ADC from 29 to 1.0 LSB after calibration. Measured results also show the signal-to-noise and distortion ratio/spurious-free dynamic range of the ADC improves from 83/94 to 96/127 dB after calibration. It will be seen that the calibration is achieved in ∼4k cycles, which is more than ×25 faster than previously published algorithm.
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