IET Circuits Devices Syst.最新文献_第4页

Design of small size and high sensitive less-invasive wireless blood pressure sensor using MEMS technology 采用MEMS技术设计小尺寸、高灵敏度、无创无线血压传感器

IET Circuits Devices Syst. Pub Date : 2018-06-13 DOI: 10.1049/iet-cds.2018.0013

Bahram Azizollah-Ganji, Sanaz Kheiry, S. Soleimani

{"title":"Design of small size and high sensitive less-invasive wireless blood pressure sensor using MEMS technology","authors":"Bahram Azizollah-Ganji, Sanaz Kheiry, S. Soleimani","doi":"10.1049/iet-cds.2018.0013","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.0013","url":null,"abstract":"This study presents an implantable passive wireless blood pressure sensor using an inductive coupling wireless sensing technique that is designed for long-term monitoring of blood pressure in hypertension patients. This sensor includes a gold tapered square spiral inductor and a circular capacitor with a polyimide diaphragm. The purpose of this study is to minimise the dimension of the sensor due to the limitation of space around the vessel; therefore, a microelectromechanical systems (MEMS) inductor and a capacitor with small dimension and high sensitivity are used. In this structure, the diaphragm is deflected by applied pressure which capacitance and then resonance frequency are changed. These changes are sensed remotely with inductive coupling, which eliminates the need of wires connection for monitoring. In this method, a blood pressure signal can be obtained by measuring the impedance phase dip from the external coil. The distance between two coils is 8 mm. The sensor is designed to provide a resonance frequency range of 282-381 MHz for a pressure range of 0-250 mmHg. Simulation has been done using COMSOL Multiphysics and ADS software. The dimension of the sensor is 2.2 mm × 2.2 mm and the sensitivity of the sensor is 1550. This sensor has a small size and high sensitivity rather than previous works.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118066796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Manchester-encoded data transmission circuit integrated by metal-oxide TFTs suitable for 13.56 MHz radio-frequency identification tag application 由金属氧化物tft集成的曼彻斯特编码数据传输电路，适用于13.56 MHz射频识别标签应用

IET Circuits Devices Syst. Pub Date : 2018-04-13 DOI: 10.1049/iet-cds.2017.0499

Jian-Dong Wu, Zhuo-Jia Chen, Jun-Sheng Wang, Lei Zhou, Weijing Wu, Miao Xu, Lei Wang, R. Yao, Junbiao Peng

引用次数: 3

Identification of DC-DC buck converter dynamics using relay feedback method with experimental validation 用继电器反馈方法辨识DC-DC降压变换器的动态特性，并进行了实验验证

IET Circuits Devices Syst. Pub Date : 2018-04-13 DOI: 10.1049/iet-cds.2017.0542

K. V. Ramana, S. Majhi, A. Gogoi

引用次数: 10

High-speed analogue sampled-data signal processing for real-time fault location in electrical power networks 用于电网实时故障定位的高速模拟采样数据信号处理

IET Circuits Devices Syst. Pub Date : 2018-03-09 DOI: 10.1049/iet-cds.2017.0212

François Gaugaz, F. Krummenacher, M. Kayal

{"title":"High-speed analogue sampled-data signal processing for real-time fault location in electrical power networks","authors":"François Gaugaz, F. Krummenacher, M. Kayal","doi":"10.1049/iet-cds.2017.0212","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0212","url":null,"abstract":"The emulation of low-loss or lossless one-dimensional (1D) or 2D transmission mediums using analogue sampled-data signal processing is presented. Based on discrete-time wave propagation simulation, transmission lines are emulated with many elementary identical delay elements, implemented by simple equivalent switched-capacitor (SC) circuits. The accuracy and limitations of this discrete time model are studied in the frame of power network fault location using electromagnetic time-reversal principle. The sensitivities to non-ideal effects usually plaguing analogue CMOS SC circuits, such as amplifier finite open-loop gain, offset, and parasitic charge injection due to clock feedthrough, are evaluated in the same context. It is shown that the SC line emulation is well suited to the presented fault location technique and considerably reduces the fault location time (by a factor up to 100) in comparison to standard digital solutions, allowing fault location resolutions of typically 1% within a few hundred milliseconds. These expectations are confirmed by measurements realised on the presented line model integrated-circuit, implemented in an AMS 0.35 μm CMOS process. The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118768143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Low-power sample and hold circuits using current conveyor analogue switches 使用电流输送模拟开关的低功耗采样和保持电路

IET Circuits Devices Syst. Pub Date : 2018-01-30 DOI: 10.1049/iet-cds.2017.0411

M. Kumngern, Thanat Nonthaputha, F. Khateb

引用次数: 6

Oscillation analysis and current peak reduction in paralleled SiC MOSFETs 并联SiC mosfet的振荡分析与电流峰值降低

IET Circuits Devices Syst. Pub Date : 2018-01-30 DOI: 10.1049/iet-cds.2017.0255

K. Nanamori, Yusuke Sugihara, Masayoshi Yamamoto

{"title":"Oscillation analysis and current peak reduction in paralleled SiC MOSFETs","authors":"K. Nanamori, Yusuke Sugihara, Masayoshi Yamamoto","doi":"10.1049/iet-cds.2017.0255","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0255","url":null,"abstract":"Parallel connection of power metal oxide semiconductor field effect transistors (MOSFETs) is often used in the high current side of power conversion systems to obtain a thermal dispersion and low conduction losses. However, a parallel connection may lead to a current unbalance due to the difference of parasitic parameters and switching characteristics of the paralleled devices. The current unbalance generates current oscillations, and in the worst case, it may lead to complete destruction of the power devices. This study analyses an inherent oscillation of two paralleled SiC MOSFETs, under current unbalance conditions. Based on the proposed analysis, it is found that the parasitic inductance is the main cause of the coupled oscillation, which is composed of two different oscillation frequencies. In this study, the coupled oscillation leads to a difference of peak currents between paralleled devices. The circuit conditions, considering the parasitic inductances, are investigated to suppress the coupled oscillation. As a result, a reduction of the common parasitic inductance allows preventing the coupled oscillation and to suppress the peak combined current of paralleled devices. Moreover, a peak current reduction by 37.8% can be achieved, as a result of eliminating the coupled oscillation.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120139470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Design of high-speed, low-power, and area-efficient FIR filters 设计高速，低功耗和面积高效的FIR滤波器

IET Circuits Devices Syst. Pub Date : 2018-01-11 DOI: 10.1049/iet-cds.2017.0058

A. Liacha, A. K. Oudjida, F. Ferguene, Mohammed Bakiri, M. L. Berrandjia

{"title":"Design of high-speed, low-power, and area-efficient FIR filters","authors":"A. Liacha, A. K. Oudjida, F. Ferguene, Mohammed Bakiri, M. L. Berrandjia","doi":"10.1049/iet-cds.2017.0058","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0058","url":null,"abstract":"In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2 r . The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2 r is more specially investigated. RADIX-2 r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2 r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2 r in high order filters.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119212982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Low-jitter DLL applied for two-segment TDC 用于两段TDC的低抖动DLL

IET Circuits Devices Syst. Pub Date : 2018-01-11 DOI: 10.1049/iet-cds.2016.0342

Jin Wu, You-Chen Zhang, Rongqi Zhao, Kunpeng Zhang, Lixia Zheng, Weifeng Sun

{"title":"Low-jitter DLL applied for two-segment TDC","authors":"Jin Wu, You-Chen Zhang, Rongqi Zhao, Kunpeng Zhang, Lixia Zheng, Weifeng Sun","doi":"10.1049/iet-cds.2016.0342","DOIUrl":"https://doi.org/10.1049/iet-cds.2016.0342","url":null,"abstract":"A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal-oxide-semiconductor process, the measurement results show that DLL's frequency locking range is 60-240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of <;1 ns and maximum range of around 1 μs as well as the differential non-linearity <;0.68 LSB and the integration non-linearity within -0.97 to 1.24 LSB are obtained for two-segment TDC.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120493275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Light activation of noise at microwave frequencies: a study on scaled gallium arsenide HEMT's 微波频率下噪声的光激活:尺度砷化镓HEMT的研究

IET Circuits Devices Syst. Pub Date : 2017-11-21 DOI: 10.1049/iet-cds.2017.0290

A. Caddemi, E. Cardillo, G. Crupi

{"title":"Light activation of noise at microwave frequencies: a study on scaled gallium arsenide HEMT's","authors":"A. Caddemi, E. Cardillo, G. Crupi","doi":"10.1049/iet-cds.2017.0290","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0290","url":null,"abstract":"This study is focused on the experimental investigation of noise at microwave frequencies for scaled gallium arsenide high-electron-mobility transistor's (HEMT's). The light activation of noise has been achieved by laser exposure in the visible range. The devices have 0.25 μm gate length and 100–200–300 μm gate widths. Their DC characteristics, linear scattering and noise parameters were measured both in dark condition and under continuous wave light exposure in the 2–18 GHz frequency range. Previous results had shown a remarkable influence on all the above-measured parameters under illumination, with a special concern for the noise performance. Therefore, the authors investigated the origin of this light-activated noise in terms of the intrinsic noise sources, by extracting a noise temperature circuit model for each HEMT.In addition, the noise model formulation based on the P, R and C as well as the K g, K r and K c coefficients is used to enlighten the key aspects of the optically activated noise on the device performance. It is observed that the degradation of the minimum noise figure can be attributed to the noise coefficient R, related to the gate noise source that is strongly affected by the charge generation related to light exposure.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120738912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Ultra-low-power, high PSRR CMOS voltage reference with negative feedback 超低功耗，高PSRR CMOS负反馈基准电压

IET Circuits Devices Syst. Pub Date : 2017-11-20 DOI: 10.1049/iet-cds.2016.0452

Yanhan Zeng, Yu-Ao Liu, Xin Zhang, Hongzhou Tan

引用次数: 12