Hardware implementation of the quasi-maximum likelihood estimator core for polynomial phase signals

Nevena R. Brnovic, I. Djurović, Veselin N. Ivanović, M. Simeunović
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引用次数: 6

Abstract

Flexible, multiple-clock-cycle, hardware design for the quasi-maximum likelihood (QML) algorithm core realisation for the polynomial phase signals (PPSs) estimation is proposed. The QML algorithm significantly outperforms existing PPS estimators in terms of accuracy. However, its practical applications require efficient software and hardware systems. The main challenges in the proposed hardware development with respect to existing systems for time–frequency (TF) analysis are realisation of TF representation based instantaneous frequency estimator, the polynomial regression, and phase extraction. The developed design is tested on a PPS corrupted by a white Gaussian noise and verified by a field programmable gate array circuit design. All implementation and verification details are provided along with the comparison of the results achieved by hardware and software implementations.
多项式相位信号拟极大似然估计器核心的硬件实现
提出了多项式相位信号估计的准极大似然(QML)算法核心实现的灵活、多时钟周期的硬件设计。QML算法在精度方面显著优于现有的PPS估计器。然而,其实际应用需要高效的软件和硬件系统。针对现有的时频(TF)分析系统,提出的硬件开发的主要挑战是基于瞬时频率估计器、多项式回归和相位提取的TF表示的实现。该设计在高斯白噪声干扰的PPS上进行了测试,并通过现场可编程门阵列电路设计进行了验证。提供了所有的实现和验证细节,并对硬件和软件实现的结果进行了比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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