Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)最新文献

Mitigating inductive noise in SMT processors 减小SMT处理器中的感应噪声

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-11-01 DOI: 10.1109/LPE.2004.241160

W. El-Essawy, D. Albonesi

引用次数: 25

Balanced energy optimization 平衡能量优化

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-09-22 DOI: 10.1145/1023833.1023835

J. Cornish

{"title":"Balanced energy optimization","authors":"J. Cornish","doi":"10.1145/1023833.1023835","DOIUrl":"https://doi.org/10.1145/1023833.1023835","url":null,"abstract":"Summary form only given. Energy efficiency is now the number one issue for many applications, determining weight and cost, and constraining system performance. Many techniques have been developed to minimize the dynamic and static power consumed by digital designs without any impact on functionality. To achieve further savings it is necessary to employ methods that do constrain functionality in some way. The designer must then balance increased energy efficiency with the functional implications of those techniques. In communications systems non-zero error rates are accommodated and corrected in order to reduce power. In digital designs it is also possible to accept and correct errors generated when worst case timing paths exceed the clock interval. This allows the design to be operated beyond the worst case point at a reduced voltage to save energy. The increased energy efficiency must then be balanced against a decrease in determinism and the addition of error detection and correction structures. Processing scalability can also be employed to increase energy efficiency for workloads which vary dynamically. In single processor system this can be achieved using voltage and frequency scaling, and in multi-processor systems this can be supplemented with adaptive shutdown of unused processors. Scalability does imply a loss of system responsiveness when workloads transition from low to high levels, and this must be balanced against the increased energy efficiency achieved. Power efficiency can also be increased by optimising a processor for the application it is intended to run. By analyzing the algorithms to be executed it is possible to create a processor tailored to its workload. This loss of generality and flexibility must be balanced against the increased energy efficiency of a customized implementation. This talk describes work which ARM and its partners are doing to balance energy efficiency with functionality to create optimized designs.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Design and implementation of correlating caches 关联缓存的设计和实现

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013255

A. Mallik, M. Wildrick, G. Memik

引用次数: 3

Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation 集成自适应DC/DC转换与自适应脉冲序列技术，实现低纹波快速响应调节

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013301

Chuang Zhang, D. Ma, A. Srivastava

引用次数: 24

Reducing pipeline energy demands with local DVS and dynamic retiming 利用局部DVS和动态重定时降低管道能量需求

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013313

Seokwoo Lee, Shidhartha Das, Toan Pham, T. Austin, D. Blaauw, T. Mudge

{"title":"Reducing pipeline energy demands with local DVS and dynamic retiming","authors":"Seokwoo Lee, Shidhartha Das, Toan Pham, T. Austin, D. Blaauw, T. Mudge","doi":"10.1145/1013235.1013313","DOIUrl":"https://doi.org/10.1145/1013235.1013313","url":null,"abstract":"The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniques such as Razor DVS, voltage overscaling, and intelligent energy management have emerged as approaches to further reduce voltage by eliminating costly voltage margins inserted into traditional designs to ensure always-correct operation. The degree to which a global voltage controller can shave voltage margins is limited by imbalances in pipeline stage latency. Since all pipeline stages share the same voltage, the stage exercising the longest critical path will define the overall voltage of the system, even if other stages could potentially run at lower voltages. In this paper, we evaluate two local tuning mechanisms in the context of Razor DVS, a local voltage controller scheme that allows each pipeline stage its own voltage level, and a lower cost dynamic retiming scheme that incorporates per-stage clock delay elements to allow longer-latency pipeline stages to \"borrow\" time from shorter-latency stages. Using simulation, we draw two key insights from our study. First, mitigating pipeline stage imbalances render additional DVS energy savings. A Razor pipeline design with dynamic retiming finds an additional 12% energy savings over global voltage control (resulting in overall energy savings of more than 28% compared to fully-margined DVS). Second, we demonstrate that imbalances arise not only from design factors, but also from run-time characteristics. As the program (or program phase) changes, we see different logic paths in multiple stages exercised frequently, necessitating a dynamic fine-tuning of local control. This result suggests that even well-balanced pipelines could benefit from dynamic retiming.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127238521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Technology exploration for adaptive power and frequency scaling in 90nm CMOS 90纳米CMOS自适应功率和频率缩放技术探索

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013245

M. Meijer, F. Pessolano, J. P. D. Gyvez

引用次数: 24

Post-layout leakage power minimization based on distributed sleep transistor insertion 基于分布式睡眠晶体管插入的布局后漏功率最小化

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013275

P. Babighian, L. Benini, A. Macii, E. Macii

引用次数: 44

Energy-aware demand paging on NAND flash-based embedded storages 基于NAND闪存的嵌入式存储的能源感知需求分页

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013317

Chanik Park, Jeong-Uk Kang, Seon-Yeong Park, Jinsoo Kim

{"title":"Energy-aware demand paging on NAND flash-based embedded storages","authors":"Chanik Park, Jeong-Uk Kang, Seon-Yeong Park, Jinsoo Kim","doi":"10.1145/1013235.1013317","DOIUrl":"https://doi.org/10.1145/1013235.1013317","url":null,"abstract":"The ever-increasing requirement for high-performance and huge-capacity memories of emerging embedded applications has led to the widespread adoption of SDRAM and NAND flash memory as main and secondary memories, respectively. In particular, the use of energy consuming memory, SDRAM, has become burdensome in battery-powered embedded systems. Intuitively, though demand paging can be used to mitigate the increasing requirement of main memory size, its applicability should be deliberately elaborated since NAND flash memory has asymmetric operation characteristics in terms of performance and energy consumption. In this paper, we present an energy-aware demand paging technique to lower the energy consumption of embedded systems considering the characteristics of interactive embedded applications with large memory footprints. We also propose a flash memory-aware page replacement policy that can reduce the number of write and erase operations in NAND flash memory. With real-life workloads, we show the system-wide energy-delay product can be reduced by 15/spl sim/30% compared to the traditional shadowing architecture.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121668247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 90

Managing standby and active mode leakage power in deep sub-micron design 管理深亚微米设计中的待机和有源模式泄漏功率

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013239

L. Clark, Rakesh J. Patel, T. Beatty

引用次数: 28

Location cache: a low-power L2 cache system 位置缓存:一个低功耗的二级缓存系统

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013271

Rui Min, W. Jone, Yimin Hu

{"title":"Location cache: a low-power L2 cache system","authors":"Rui Min, W. Jone, Yimin Hu","doi":"10.1145/1013235.1013271","DOIUrl":"https://doi.org/10.1145/1013235.1013271","url":null,"abstract":"While set-associative caches incur fewer misses than direct-mapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are probed in parallel. This paper presents the location cache structure which significantly reduces the power consumption for large set-associative caches. We propose to use a small cache, called location cache to store the location of future cache references. If there is a hit in the location cache, the supported cache is accessed as a direct-mapped cache. Otherwise, the supported cache is referenced as a conventional set-associative cache. The worst case access latency of the location cache system is the same as that of a conventional cache. The location cache is virtually indexed so that operations on it can be performed in parallel with the TLB address translation. These advantages make it ideal for L2 cache systems where traditional way-predication strategies perform poorly. We used the CACTI cache model to evaluate the power consumption and access latency of proposed cache architecture. Simplescalar CPU simulator was used to produce final results. It is shown that the proposed location cache architecture is power-efficient. In the simulated cache configurations, up-to 47% of cache accessing energy and 25% of average cache access latency can be reduced.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133881562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 38