管理深亚微米设计中的待机和有源模式泄漏功率

L. Clark, Rakesh J. Patel, T. Beatty
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引用次数: 28

摘要

缩放使得每个芯片的晶体管数量不断增加,漏率呈指数级增长,使得功率成为所有集成电路设计的主要限制因素。未来的设计必须解决由于直接带到带隧道,通过MOSFET氧化物和陡峭的结掺杂梯度而出现的泄漏元件。在本文中,我们描述了管理待机期间泄漏功率和限制主动工作期间泄漏功率贡献的电路设计技术。研究了不同方法的功效、设计努力和过程分支。这些方案主要针对手机等手持设备,因为由于电池容量有限,这些市场对低功耗的需求最为迫切。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Managing standby and active mode leakage power in deep sub-micron design
Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.
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