Design and implementation of correlating caches

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI:10.1145/1013235.1013255

A. Mallik, M. Wildrick, G. Memik

{"title":"Design and implementation of correlating caches","authors":"A. Mallik, M. Wildrick, G. Memik","doi":"10.1145/1013235.1013255","DOIUrl":null,"url":null,"abstract":"We introduce a new cache architecture that can be used to increase performance and reduce energy consumption in Network Processors. This new architecture is based on the observation that there is a strong correlation between different memory accesses. In other words, if load X and load Y are two consecutively executed load instructions, the offset between the source addresses of these instructions remain usually constant between different iterations. We utilize this information by building a correlating cache architecture. This architecture consists of a Dynamic Correlation Extractor, a Correlation History Table, and a Correlation Buffer. We first show simulation results investigating the frequency of correlating loads. Then, we evaluate our architecture using SimpleScalar/ARM. For a set of representative applications, the correlating cache architecture is able to reduce the average data access time by as much as 52.7% and 36.1/% on average, while reducing the energy consumption of the caches by as much as 49.2% and 25.7% on average.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1013235.1013255","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

Abstract

We introduce a new cache architecture that can be used to increase performance and reduce energy consumption in Network Processors. This new architecture is based on the observation that there is a strong correlation between different memory accesses. In other words, if load X and load Y are two consecutively executed load instructions, the offset between the source addresses of these instructions remain usually constant between different iterations. We utilize this information by building a correlating cache architecture. This architecture consists of a Dynamic Correlation Extractor, a Correlation History Table, and a Correlation Buffer. We first show simulation results investigating the frequency of correlating loads. Then, we evaluate our architecture using SimpleScalar/ARM. For a set of representative applications, the correlating cache architecture is able to reduce the average data access time by as much as 52.7% and 36.1/% on average, while reducing the energy consumption of the caches by as much as 49.2% and 25.7% on average.

查看原文本刊更多论文

关联缓存的设计和实现

我们介绍了一种新的缓存架构，可用于提高网络处理器的性能并降低能耗。这种新的体系结构是基于观察到不同的内存访问之间存在很强的相关性。换句话说，如果加载X和加载Y是两个连续执行的加载指令，则这些指令的源地址之间的偏移量在不同迭代之间通常保持不变。我们通过构建相关的缓存架构来利用这些信息。该体系结构由一个动态关联提取器、一个关联历史表和一个关联缓冲区组成。我们首先展示了研究相关负载频率的模拟结果。然后，我们使用SimpleScalar/ARM来评估我们的架构。对于一组具有代表性的应用程序，相关缓存架构能够将平均数据访问时间分别减少52.7%和36.1% /%，同时将缓存的能耗平均降低49.2%和25.7%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

自引率

0.00%

发文量