Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation

Abstract

Dynamic voltage scaling (DVS) is a very effective low-power design technique in modem digital IC systems. On-chip adaptive DC/DC converter, which provides adjustable output voltage, is a key component in implementing DVS-enabled system. This paper presents a new adaptive DC/DC converter design, which adopts a delay-line controller for voltage regulation. With a proposed adaptive pulse-train technique, ripple voltages are reduced by 50%, while the converter still maintains satisfying transient response. With a supply voltage of 3.3V, the output of the converter is well regulated from 1.7 to 3.0V. Power consumption of the controller is below 100 /spl mu/W. Maximum efficiency of 92% is achieved with output power of 125mW. Chip area is 0.8 /spl times/ 1.2mm/sup 2/ in 1.5 /spl mu/m standard CMOS process.