位置缓存:一个低功耗的二级缓存系统

Rui Min, W. Jone, Yimin Hu
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引用次数: 38

摘要

虽然集合关联缓存比直接映射缓存产生更少的错误,但当并行探测多个标记和数据库时,它们通常具有更慢的命中时间和更高的功耗。本文提出了一种能够显著降低大型集合关联缓存功耗的位置缓存结构。我们建议使用一个小缓存,称为位置缓存来存储未来缓存引用的位置。如果在位置缓存中有命中,则支持的缓存将作为直接映射的缓存访问。否则,支持的缓存被引用为常规的集关联缓存。位置缓存系统的最坏情况访问时延与传统缓存相同。位置缓存是虚拟索引的,因此对它的操作可以与TLB地址转换并行执行。这些优点使其成为L2缓存系统的理想选择,在这些系统中,传统的方式预测策略表现不佳。我们使用CACTI缓存模型来评估所提出的缓存架构的功耗和访问延迟。使用Simplescalar CPU模拟器生成最终结果。实验结果表明,所提出的位置缓存架构是高效节能的。在模拟的缓存配置中,最多可以减少47%的缓存访问能量和25%的平均缓存访问延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than direct-mapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are probed in parallel. This paper presents the location cache structure which significantly reduces the power consumption for large set-associative caches. We propose to use a small cache, called location cache to store the location of future cache references. If there is a hit in the location cache, the supported cache is accessed as a direct-mapped cache. Otherwise, the supported cache is referenced as a conventional set-associative cache. The worst case access latency of the location cache system is the same as that of a conventional cache. The location cache is virtually indexed so that operations on it can be performed in parallel with the TLB address translation. These advantages make it ideal for L2 cache systems where traditional way-predication strategies perform poorly. We used the CACTI cache model to evaluate the power consumption and access latency of proposed cache architecture. Simplescalar CPU simulator was used to produce final results. It is shown that the proposed location cache architecture is power-efficient. In the simulated cache configurations, up-to 47% of cache accessing energy and 25% of average cache access latency can be reduced.
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