Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Abstract

In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modem deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Measurement results indicate that it is possible to reach 13.8/spl times/ power savings by 3.4/spl times/ frequency downscaling using AVS, /spl plusmn/11% power and /spl plusmn/8% frequency tuning at nominal conditions using ABB only, 22/spl times/ power savings with 5/spl times/ frequency downscaling by combining AVS and ABB, as well as 22/spl times/ leakage reduction.