Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)最新文献_第2页

Impact of technology scaling on energy aware execution cache-based microarchitectures 技术扩展对基于能量感知执行缓存的微架构的影响

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013253

Emil Talpes, Diana Marculescu

引用次数: 2

Subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations 考虑模内和模间P-T-V变化的亚阈值泄漏功率分布

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013278

Songqing Zhang, V. Wason, K. Banerjee

{"title":"Subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations","authors":"Songqing Zhang, V. Wason, K. Banerjee","doi":"10.1145/1013235.1013278","DOIUrl":"https://doi.org/10.1145/1013235.1013278","url":null,"abstract":"This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSlM results and are found to he more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114319487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems 评估和优化RFID系统中防碰撞协议的功耗

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013321

F. Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min

引用次数: 193

Dynamic power management for streaming data 流数据的动态电源管理

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013256

N. Pettis, Le Cai, Yung-Hsiang Lu

引用次数: 15

Dynamic voltage and frequency scaling based on workload decomposition 基于工作负载分解的动态电压和频率缩放

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013282

Kihwan Choi, R. Soma, Massoud Pedram

{"title":"Dynamic voltage and frequency scaling based on workload decomposition","authors":"Kihwan Choi, R. Soma, Massoud Pedram","doi":"10.1145/1013235.1013282","DOIUrl":"https://doi.org/10.1145/1013235.1013282","url":null,"abstract":"This paper presents a technique called \"workload decomposition\" in which the CPU workload is decomposed in two parts: on-chip and off-chip. The on-chip workload signifies the CPU clock cycles that are required to execute instructions in the CPU whereas the off-chip workload captures the number of external memory access clock cycles that are required to perform external memory transactions. When combined with a dynamic voltage and frequency scaling (DVFS) technique to minimize the energy consumption, this workload decomposition method results in higher energy savings. The workload decomposition itself is performed at run time based on statistics reported by a performance monitoring unit (PMU) without a need for application profiling or compiler support. We have implemented the proposed DVFS with workload decomposition technique on the BitsyX platform, an Intel PXA255-based platform manufactured by ADS Inc., and performed detailed energy measurements. These measurements show that, for a number of widely used software applications, a CPU energy saving of 80% can be achieved for memory-bound programs while satisfying the user-specified timing constraints.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121022213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 226

Application-level prediction of battery dissipation 应用级电池耗散预测

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013292

C. Krintz, Ye Wen, R. Wolski

引用次数: 55

Battery life challenges on future mobile notebook platforms 未来移动笔记本平台的电池寿命挑战

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013238

S. Thakkar

{"title":"Battery life challenges on future mobile notebook platforms","authors":"S. Thakkar","doi":"10.1145/1013235.1013238","DOIUrl":"https://doi.org/10.1145/1013235.1013238","url":null,"abstract":"Summary form only given. With the introduction of Intel/spl reg/ Centrino/spl trade/ Mobile Technology in 2003, Intel redefined mobile computing to deliver the outstanding mobile performance, integrated wireless capability, while enabling extended battery life and thin and light designs that end users demand. In developing Intel Centrino Mobile Technology, Intel took an aggressive goal of enabling at least 3.5 hours (210 minutes) of battery life given typical usage of \"thin and light\" class notebooks with 6-cell lithium ion batteries. Compared with Intel/spl reg/ Pentium/spl reg/ 4 processor-M-based systems, this would be at least an hour more battery life. This goal was exceeded by the majority of the Intel Centrino mobile technology-based notebooks introduced at the launch in March 2003, with these notebooks delivering some of the longest battery run times available on mobile PCs. However, the industry is facing new challenges. Current battery technologies are topping out in capacity, while demands for new mobile PC capabilities and higher performance are driving higher average power consumption. This talk will address the opportunity to innovate on lower power silicon and platform designs as well as higher density and renewable power sources to enable 8-hour or greater battery life for \"all-day\" computing. Techniques used today to deliver lower average power at the silicon as well as platform levels will be discussed, (e.g., voltage and frequency scaling techniques are use in today's silicon to provide performance-on-demand while consuming lowest average power when the processor is idle, lower power display technologies such as LTPS reduce power by at least 30% over conventional displays) as well as alternative battery chemistries that may deliver higher capacity and renewable/quick rechargeable sources will also be discussed.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132281731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems 实时嵌入式系统中全系统能量最小化的动态电压缩放

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013261

R. Jejurikar, Rajesh K. Gupta

引用次数: 182

Understanding nanoscale conductors 了解纳米级导体

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013240

S. Datta

{"title":"Understanding nanoscale conductors","authors":"S. Datta","doi":"10.1145/1013235.1013240","DOIUrl":"https://doi.org/10.1145/1013235.1013240","url":null,"abstract":"Summary form only given. It is common to differentiate between two ways of building a nanodevice: a top-down approach where we start from something big and chisel out what we want and a bottom-up approach where we start from something small like atoms or molecules and assemble what we want. When it comes to describing electrical resistance, the standard approach could be called a \"top-down\" one where we start from large complex resistors and work our way down to molecules primarily because our understanding has evolved in this top-down fashion. However, it is instructive to take a bottom-up view of the subject starting from the conductance of something really small, like a molecule, and then discussing the issues that arise as we move to bigger conductors. This is the subject of this tutorial lecture (S. Datta, Nanotechnology, vol. 15, p. S433, 2004). Remarkably enough, no serious quantum mechanics is needed to understand electrical conduction through something really small, except for unusual things like the Kondo effect that are seen only for a special range of parameters. The presentation begins with (1) energy level diagrams, (2) shows that the broadening that accompanies coupling limits the conductance to a maximum of (q¿2/h) per level, (3) describes how a change in the shape of the self-consistent potential profile can turn a symmetric current-voltage characteristic into a rectifying one, (4) shows that many interesting effects in \"nanoelectronics\" can be understood in terms of a simple model, and (5) introduces the nonequilibrium Green's function (NEGF) formalism as a sophisticated version of this simple model with ordinary numbers replaced by appropriate matrices. Finally the distinction between the self-consistent field regime and the Coulomb blockade regime and the issues involved in modeling each of these regimes are described.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116014364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors 4t衰减传感器:一种新型的小型、快速、坚固、低功耗、温度/泄漏传感器

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013268

S. Kaxiras, Polychronis Xekalakis

{"title":"4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors","authors":"S. Kaxiras, Polychronis Xekalakis","doi":"10.1145/1013235.1013268","DOIUrl":"https://doi.org/10.1145/1013235.1013268","url":null,"abstract":"We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cells to measure on-chip temperature and leakage. Using the dependence of leakage currents to temperature, we measure varying decay (discharge) times of the 4T cell at different temperatures. Thus, decaying 4T sensors provide a digital pulse whose frequency depends on temperature. Because of the sensors' very small size, we can easily embed them in many structures thus obtaining both redundancy and a fine-grain thermal picture of the chip. A significant advantage of our sensor design is that it is insensitive to process variations at high temperatures. It is also relatively robust to noise. We propose mechanisms to measure temperature that exploit the sensor's small size and speed to increase measurement reliability. Decaying 4T sensors also provide a measurement of the level of leakage at their sensing area, allowing us to adjust leakage-control policies. Our 4T sensors are significantly smaller, faster, more reliable, and power efficient compared to the best previously proposed designs enabling new approaches to architectural-level thermal and leakage management.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120968599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27