Impact of technology scaling on energy aware execution cache-based microarchitectures

Emil Talpes, Diana Marculescu
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引用次数: 2

Abstract

Reducing total power consumption in high performance microprocessors can be achieved by limiting the amount of logic involved in decoding, scheduling and executing each instruction. One of the solutions to this problem involves the use of a microarchitecture based on an Execution Cache (EC) whose role is to cache already done work for later reuse. In this paper, we explore the design space for such a microarchitecture, looking at how the cache size, associativity and replacement algorithm affect the overall performance and power efficiency. We also look at the scalability of this solution across next process generations, evaluating the energy efficiency of such caching mechanisms in the presence of increasing leakage power. Over a spectrum of SPEC2000 benchmarks, an average of 35% energy reduction is achieved for technologies ranging from 130nm to 90nm and 65nm, at the expense of a negligible performance hit.
技术扩展对基于能量感知执行缓存的微架构的影响
降低高性能微处理器的总功耗可以通过限制解码、调度和执行每条指令所涉及的逻辑量来实现。此问题的解决方案之一涉及使用基于执行缓存(EC)的微体系结构,其作用是缓存已完成的工作以供以后重用。在本文中,我们探讨了这种微架构的设计空间,研究了缓存大小、结合性和替换算法如何影响整体性能和功耗效率。我们还研究了该解决方案跨下一代进程的可扩展性,在泄漏功率不断增加的情况下评估此类缓存机制的能源效率。在SPEC2000的基准测试中,从130nm到90nm和65nm的技术平均降低了35%的能量,而性能的损失可以忽略不计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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