Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)最新文献_第3页

Delay optimal low-power circuit clustering for FPGAs with dual supply voltages 双电源电压fpga的延迟优化低功耗电路聚类

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013259

Deming Chen, J. Cong

引用次数: 24

Active mode leakage reduction using fine-grained forward body biasing strategy 采用细粒度前向体偏置策略减少有源模式泄漏

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013277

Vishal Khandelwal, Ankur Srivastava

引用次数: 21

Power utility maximization for multiple-supply systems by a load-matching switch 通过负载匹配开关实现多电源系统的电力效用最大化

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013281

Chulsung Park, P. Chou

引用次数: 57

Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization 通过微结构电压控制反馈和动态优化消除电压突发事件

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013315

K. Hazelwood, D. Brooks

{"title":"Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization","authors":"K. Hazelwood, D. Brooks","doi":"10.1145/1013235.1013315","DOIUrl":"https://doi.org/10.1145/1013235.1013315","url":null,"abstract":"Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations that stress the power-delivery network. Recent research has focused on hardware-only mechanisms to detect and eliminate these fluctuations. While the solutions have been effective at avoiding operating-range violations, they have done so at a performance penalty to the executing program. Compilers are well equipped to rearrange instructions such that current fluctuations are less dramatic, with minimal performance implications. Furthermore, a dynamic optimizer can eliminate the problem at run time, avoiding the difficult task of statically predicting voltage emergencies. This paper proposes complementing existing hardware solutions with additional run-time software to address problematic code sequences that cause recurring voltage swings. Our proposal extends existing hardware techniques to additionally provide feedback to a dynamic optimizer, which can provide a long-term solution, often without impacting the performance of the executing application. We found that recurring voltage fluctuations do exist in the SPEC2000 benchmarks, and that given very little information from the hardware, a dynamic optimizer can locate and correct many of the recurring voltage emergencies.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131279327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43

Preemption-aware dynamic voltage scaling in hard real-time systems 硬实时系统中感知抢占的动态电压缩放

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013328

Woonseok Kim, Jihong Kim, S. Min

引用次数: 80

Improved clock-gating through transparent pipelining 通过透明管道改进时钟门控

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013248

H. Jacobson

引用次数: 45

Efficient adaptive voltage scaling system through on-chip critical path emulation

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013325

M. Elgebaly, M. Sachdev

引用次数: 33

Soft error and energy consumption interactions: a data cache perspective 软错误和能耗交互:数据缓存透视图

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013273

Lin Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir, M. J. Irwin

{"title":"Soft error and energy consumption interactions: a data cache perspective","authors":"Lin Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir, M. J. Irwin","doi":"10.1145/1013235.1013273","DOIUrl":"https://doi.org/10.1145/1013235.1013273","url":null,"abstract":"Energy-efficiency and reliability are two major design constraints influencing next generation system designs. In this work, we focus on the interaction between power consumption and reliability considering the on-chip data caches. First, we investigate the impact of two commonly used architectural-level leakage reduction approaches on the data reliability. Our results indicate that the leakage optimization techniques can have very different reliability behavior as compared to an original cache with no leakage optimizations. Next, we investigate on providing data reliability in an energy-efficient fashion in the presence of soft-errors. In contrast to current commercial caches that treat and protect all data using the same error detection/correction mechanism, we present an adaptive error coding scheme that treats dirty and clean data cache blocks differently. Furthermore, we present an early-write-back scheme that enhances the ability to use a less powerful error protection scheme for a longer time without sacrificing reliability. Experimental results show that proposed schemes, when used in conjunction, can reduce dynamic energy of error protection components in L1 data cache by 11% on average without impacting the performance or reliability.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125498136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 138

Minimizing power consumption and complexity in a programmable transmit filter bank for OFDM 最大限度地降低功耗和复杂性的可编程传输滤波器组OFDM

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013293

A. Mehrnia, B. Daneshrad

引用次数: 3

Architecting voltage islands in core-based system-on-a-chip designs 在基于核心的片上系统设计中构建电压岛

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013283

Jingcao Hu, Youngsoo Shin, N. Dhanwada, R. Marculescu

引用次数: 142