Architecting voltage islands in core-based system-on-a-chip designs

Jingcao Hu, Youngsoo Shin, N. Dhanwada, R. Marculescu
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引用次数: 142

Abstract

Voltage islands enable core-level power optimization for System-on-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves island partition creation, voltage level assignment and floorplanning. The task of island partition creation and level assignment have to be done simultaneously in a floorplanning context due to the physical constraints involved in the design process. This leads to a floorplanning problem formulation that is very different from the traditional floorplanning for ASIC-style design. In this paper, we define the problem of architecting voltage islands in core-based designs and present a new algorithm for simultaneous voltage island partitioning, voltage level assignment and physical-level floorplanning. Application of the proposed algorithm to a few benchmark and industrial examples is demonstrated using a prototype tool. Results show power savings of 14%-28%, depending on the constraints imposed on the number of voltage islands and other physical-level parameters.
在基于核心的片上系统设计中构建电压岛
电压岛通过为每个核心使用独特的电源电压,实现了芯片系统(SoC)设计的核心级功率优化。电压岛的设计涉及岛屿分区创建、电压等级分配和平面规划。由于设计过程中的物理限制,岛屿分区的创建和水平分配的任务必须在平面规划的背景下同时完成。这就导致了与asic风格设计的传统平面规划有很大不同的平面规划问题。在本文中,我们定义了在基于核心的设计中构建电压岛的问题,并提出了一种同时进行电压岛划分、电压电平分配和物理层平面规划的新算法。利用原型工具对该算法进行了一些基准和工业实例的应用。结果显示,根据对电压岛的数量和其他物理级参数的限制,可以节省14%-28%的功率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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