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Euro ASIC '91最新文献

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Timing driven pin assignment in a hierarchical design environment 分级设计环境中时序驱动的引脚分配
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212865
G. Meixner, G. Zimmermann
{"title":"Timing driven pin assignment in a hierarchical design environment","authors":"G. Meixner, G. Zimmermann","doi":"10.1109/EUASIC.1991.212865","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212865","url":null,"abstract":"Presents a method for taking into account timing constraints during pin assignment, a subtask of floorplanning. Previous approaches to the pin assignment problem determine pin positions or admissible intervals on the block perimeters with the lengths of the respective nets as the only objective. Th authors describe a delay model for hierarchical combinational circuits which defines a linkage between the pins of different global nets in terms of timing dependencies. Based on this model they propose a slack optimization algorithm, which optimizes pin positions and routes for the global nets with respect to the timing requirements.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130957678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integrating verification testing and logic synthesis 集成验证测试和逻辑综合
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212844
W. Murzyn, A. Krasniewski
{"title":"Integrating verification testing and logic synthesis","authors":"W. Murzyn, A. Krasniewski","doi":"10.1109/EUASIC.1991.212844","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212844","url":null,"abstract":"In this paper, a new design strategy, in which built-in self test (BIST) synthesis tightly interacts with the functional logic design, is described. The authors' method is aimed at VLSI combinational circuits. The BIST design procedure is based on the concept of verification testing. Compared to circuits obtained using conventional design methods, they obtain a reduction in the test signals required and, as a consequence, a substantial reduction in test length and in the complexity of the built-in test pattern generator.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133376845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Processor chip design on submicron ASICs 基于亚微米asic的处理器芯片设计
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212893
H. Schettler
{"title":"Processor chip design on submicron ASICs","authors":"H. Schettler","doi":"10.1109/EUASIC.1991.212893","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212893","url":null,"abstract":"The processor chip set of the Low End ES/9000 is implemented on five CMOS VLSI Chips containing 2.8 Million transistors with an effective channel length of 0.5 mu m. The chips are packaged on multi-chip and single-chip modules. The worst case operating frequency is 35 MHz. The experience gained during the design of this processor is used to extrapolate into submicron technology down to 0.25 mu m. The result is the expectation of a tremendous density and performance increase within the next decade.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121460826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Power calculation for high density CMOS gate arrays 高密度CMOS门阵列的功率计算
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212867
W. Eisenmann, M. Kohl
{"title":"Power calculation for high density CMOS gate arrays","authors":"W. Eisenmann, M. Kohl","doi":"10.1109/EUASIC.1991.212867","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212867","url":null,"abstract":"Describes a new procedure to calculate the power dissipation of CMOS circuits. The system is based on a predefined energy dissipation library taking into account all dynamic power components. For a specific design first the required circuit data will be calculated and then the toggle frequencies for all macro instances are determined through logical simulation. Using this data the power calculator POWCAL derives the total power consumption of every instance and for the whole design automatically.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116063756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A mixed-mode ASIC for interface control of smart-card parcmeter 一种用于智能卡参数接口控制的混合模式专用集成电路
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212881
E. Compagne, F. Ilie
{"title":"A mixed-mode ASIC for interface control of smart-card parcmeter","authors":"E. Compagne, F. Ilie","doi":"10.1109/EUASIC.1991.212881","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212881","url":null,"abstract":"CIPAF is a microcontroller's peripheral ASIC working on a two wires serial bus. It implements functions of the smart-card parcmeter PIAF, the first on-board car parcmeter. PIAF has a pocket calculator size, is battery powered and parking fees are charged on a smart card. CIPAF mainly controls LCD display, power supply batteries, ambient temperature measurement for accurate real-time clock generation and includes the low-power part of voltage elevators required for reading and writing into smart cards. It also generates a 1 MHz clock for the microcontroller. Size and cost reduction dictate the fewest external components possible which in turn impose to CIPAF using a new solution for ESD protection on its pins in contact with the smart card. The solution has been patented. A mixed-mode analog-digital implementation was the only way for meeting both low power consumption and high accuracy requirements.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"69 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131520868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CMOS video cameras CMOS摄像机
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212885
G. Wang, D. Renshaw, P. Denyer, M. Lu
{"title":"CMOS video cameras","authors":"G. Wang, D. Renshaw, P. Denyer, M. Lu","doi":"10.1109/EUASIC.1991.212885","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212885","url":null,"abstract":"A single chip CMOS video camera is presented, along with design technique and characterization results. The chip comprises a 312*287 pixel photodiode array together with all the necessary sensing, addressing and amplifying circuitry, as well as a 1000 gate logic processor, which implements synchronization timing to deliver a fully-formatted composite video signal and a further 1000 gate logic processor, which implements automatic exposure control over a wide range. There are also simple solutions for gamma correction and test.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"4173 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127566793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
KISS-16: realization of a DSP optimized for digital mobile radio systems KISS-16:为数字移动无线电系统优化的DSP实现
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212898
H. Sahm, J. Schuck, H. Ebert, D. Weinsziehr, J. Preißner, G. Mahlich
{"title":"KISS-16: realization of a DSP optimized for digital mobile radio systems","authors":"H. Sahm, J. Schuck, H. Ebert, D. Weinsziehr, J. Preißner, G. Mahlich","doi":"10.1109/EUASIC.1991.212898","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212898","url":null,"abstract":"Presents the design strategy applied in order to develop the architecture and to realize an ASIC DSP, which is capable of performing all digital baseband algorithms for a GSM Mobile within one VLSI ASIC.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124276356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Comprehensive CAD support for boundary scan implementation in ASICs 全面的CAD支持边界扫描在asic实现
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212852
P. Lestrat, R. Leveugle, P. Magarshack
{"title":"Comprehensive CAD support for boundary scan implementation in ASICs","authors":"P. Lestrat, R. Leveugle, P. Magarshack","doi":"10.1109/EUASIC.1991.212852","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212852","url":null,"abstract":"The authors review the complete automated implementation of the IEEE P1149.1 boundary scan standard proposed in the CSAM ASIC compiled technology-independent library based on the GDT/GENESIL silicon compiler environments. The advantage of this compiled approach is to provide a flexible set of boundary scan cells, including pads and test access port (TAP) controllers. The boundary scan register is automatically created when compiling the pad ring and different parameterized function complexities allow easily the dedication of the TAP controller to any application. The user-defined elements implementation is also supported, especially by means of logic synthesis, and a test vector generation tool allows one to automatically generate the serial boundary scan test vectors from the parallel test vectors defined for the manufacturing test of the circuit. The cost of boundary scan integration has shown to be reasonable in the manufactured chips.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116724306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
ASIC chip set development for PCM 2 and 3-ary group MUX and DEMUX with EIS project 基于EIS项目的pcm2和3元组MUX和DEMUX的ASIC芯片组开发
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212849
Liang Jie
{"title":"ASIC chip set development for PCM 2 and 3-ary group MUX and DEMUX with EIS project","authors":"Liang Jie","doi":"10.1109/EUASIC.1991.212849","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212849","url":null,"abstract":"The author describes a two ASICs design of a PCM 2 and 3-ary group multiplexer and demultiplexer based on the VENUS-S system. The ASIC chip set meets the requirements of multiplex equipment and is in accord with CCITT recommendations. A positive justification circuit had been adopted. HDB3 encoder/decoder and system fault alarm circuit are internal. Measurement of the system shows that the performance of the equipment which uses a MUX/DEMUX ASIC is better than the old one. Its power consumption is less than 14 W for 3-ary and 3.5 W for 2-ary.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127882764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VLSI chip set for floating point vector processing 用于浮点向量处理的VLSI芯片组
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212875
A. Laudenbach, M. Glesner, P. Windirsch, J. Plahl, W. Clemens
{"title":"VLSI chip set for floating point vector processing","authors":"A. Laudenbach, M. Glesner, P. Windirsch, J. Plahl, W. Clemens","doi":"10.1109/EUASIC.1991.212875","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212875","url":null,"abstract":"In a long term research project a floating point vector processor for applications in automotive control has been developed. With the vector processor a thermodynamical evaluation of each combustion will be possible in real time. The arithmetic units and the on-chip vector memory have been designed in student's projects. These parts are fabricated in an industrial 1.2 mu m CMOS technology as single chips on one wafer. The design, test results, and the concept of system integration of the vector processor are presented.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127196294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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