基于EIS项目的pcm2和3元组MUX和DEMUX的ASIC芯片组开发

Euro ASIC '91 Pub Date : 1991-05-27 DOI:10.1109/EUASIC.1991.212849

Liang Jie

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引用次数: 1

摘要

本文介绍了一种基于VENUS-S系统的pcm2和3元组复用器和解复用器的双asic设计。ASIC芯片组满足多路复用设备的要求，符合CCITT的建议。采用了一种正校验电路。内部配置HDB3编/解码器和系统故障报警电路。系统测试表明，采用MUX/DEMUX ASIC的设备性能优于旧的设备。其功耗小于14w的3-ary和3.5 W的2-ary

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ASIC chip set development for PCM 2 and 3-ary group MUX and DEMUX with EIS project

The author describes a two ASICs design of a PCM 2 and 3-ary group multiplexer and demultiplexer based on the VENUS-S system. The ASIC chip set meets the requirements of multiplex equipment and is in accord with CCITT recommendations. A positive justification circuit had been adopted. HDB3 encoder/decoder and system fault alarm circuit are internal. Measurement of the system shows that the performance of the equipment which uses a MUX/DEMUX ASIC is better than the old one. Its power consumption is less than 14 W for 3-ary and 3.5 W for 2-ary.<>

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Euro ASIC '91

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