发布求助
文献互助 智能选刊 最新文献

Euro ASIC '91最新文献

筛选
英文 中文
A digital CMOS fully connected neural network with in-circuit learning capability and automatic identification of spurious attractors 一种数字式CMOS全连接神经网络，具有在线学习能力和虚假吸引子自动识别能力
Euro ASIC '91 Pub Date : 1991-07-08 DOI: 10.1109/IJCNN.1991.155576
J. Gascuel, M. Weinfeld, S. Chakroun
{"title":"A digital CMOS fully connected neural network with in-circuit learning capability and automatic identification of spurious attractors","authors":"J. Gascuel, M. Weinfeld, S. Chakroun","doi":"10.1109/IJCNN.1991.155576","DOIUrl":"https://doi.org/10.1109/IJCNN.1991.155576","url":null,"abstract":"Describes a completely connected feedback network with 64 binary neurons, using digital CMOS technology. The architecture implements a linear systolic loop, in which each neuron stores locally its own synaptic coefficients, and the potential calculation needs N time steps, each performing N partial weighted sums, to realize the N/sup 2/ operations needed. It implements internal learning capabilities, using the Widrow-Hoff rule, which converges towards the pseudo-inverse rule by iteration, thus allowing partial correlation between prototypes, and a higher capacity, compared to the Hebb rule. Also, it implements an internal mechanism for detecting relaxations on spurious states. The average retrieval speed is about 20 mu s, whereas the learning time is approximately 15 to 30 ms for 15 moderately correlated prototypes.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134516897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Resource assignment with different target architectures 不同目标体系结构的资源分配
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212871
A. Mignotte, M. Paulet
{"title":"Resource assignment with different target architectures","authors":"A. Mignotte, M. Paulet","doi":"10.1109/EUASIC.1991.212871","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212871","url":null,"abstract":"A flexible approach for resource assignment is presented. This approach may be applied to bus based or MUX based target architectures with various options on the optimization criteria and constraints.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121823304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
SICURE-a crypto chip for rapid encipherment 一种用于快速加密的加密芯片
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212891
H.M. Deppermann, J. Gessner, S. Kosters, S. Wallstab
{"title":"SICURE-a crypto chip for rapid encipherment","authors":"H.M. Deppermann, J. Gessner, S. Kosters, S. Wallstab","doi":"10.1109/EUASIC.1991.212891","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212891","url":null,"abstract":"The crypto chip SICURE (Siemens coprocessor unit for rapid encipherment) is a cryptographic coprocessor designed for the protection of sensitive data. The implemented DES (data encryption standard) and other proprietary symmetric block ciphers achieve confidentiality and integrity of messages. A data flow rate of more than 20 Mb/s makes it well-suited for local area networks or hard disk controller applications.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"449 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124283023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
G2L: system for converting low-level geometrical designs to a higher level representation G2L:将低级几何设计转换为高级表示的系统
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212835
E. Pajarre, T. Ritoniemi, H. Tenhunen
{"title":"G2L: system for converting low-level geometrical designs to a higher level representation","authors":"E. Pajarre, T. Ritoniemi, H. Tenhunen","doi":"10.1109/EUASIC.1991.212835","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212835","url":null,"abstract":"The author presents a methodology for converting VLSI design information from a geometry oriented database to a higher level database where electrical objects are the primitive elements. The conversion extracts the active elements and implicit connections from the geometry and recreates them using novel routing techniques producing geometrically identical layout. The methodology has been implemented in a GDS II to L language converter capable of converting databases containing whole chip designs. The system has been tested with processor designs and whole standard cell libraries.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121638234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
UDL/I standardization effort another approach to HDL standard UDL/I标准化工作是HDL标准的另一种方法
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212831
O. Karatsu
{"title":"UDL/I standardization effort another approach to HDL standard","authors":"O. Karatsu","doi":"10.1109/EUASIC.1991.212831","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212831","url":null,"abstract":"UDL/I (Unified Design Language for Integrated circuits) is a hardware design language (HDL) for VLSI design. It was developed in Japan by a standardization committee that consists of over 30 companies, universities and related organizations. One-third of the members are non-Japanese. UDL/I is a logic synthesis oriented design language that (1) provides a formal and strict semantic definition, (2) supports a high level construct for a case in hardware description, and (3) allows quick and error-free design. The committee completed the language reference manual for the first version in 1990 and will provide typical UDL/I processors (i.e. a compiler, a simulator and so on) for trial runs by the end of March, 1992. A standardized HDL will contribute to the area of high level design and will coexist in the CAD environment with VHDL to cover the different aspects of hardware design activity.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"67 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132360031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Pipeline based design for numerically controlled oscillator 基于流水线的数控振荡器设计
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212873
Ji Lijiu, Li Dina, Lian Qinglin, Sheng Shimin
{"title":"Pipeline based design for numerically controlled oscillator","authors":"Ji Lijiu, Li Dina, Lian Qinglin, Sheng Shimin","doi":"10.1109/EUASIC.1991.212873","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212873","url":null,"abstract":"With analyzing features of the accumulator in numerically controlled oscillator (NCO), it is pointed out that design based on pipeline for NCO is feasible. The schematic and results of logic simulation are given in this paper. The pipeline based NCO has evidently more advantages: higher speed (about twice) and fewer components (about 2/3) than usual.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114766492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application example of multi-level digital design verification by the SFG-tracing methodology sfg跟踪方法在多级数字设计验证中的应用实例
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212833
L. Claesen, M. Genoe, E. Verlind, F. Proesmans, H. de Man
{"title":"Application example of multi-level digital design verification by the SFG-tracing methodology","authors":"L. Claesen, M. Genoe, E. Verlind, F. Proesmans, H. de Man","doi":"10.1109/EUASIC.1991.212833","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212833","url":null,"abstract":"In this paper a novel methodology for the formal correctness verification of digital (VLSI) designs is presented. This methodology aims at bridging the gap from transistor switch level circuits, as obtained from circuit extraction, up to high level specifications. The SFG-tracing verification methodology inherits its power from the exploitation of the inherent algorithmic information in the high level (signal flow graph level) specifications. Given the fact that the circuit designer provides the appropriate reference signals and mapping functions, the methodology is intended to operate automatically on VLSI circuits of up to 50000 transistors and more.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121893820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An efficient program for logic synthesis of mod-2 sum expressions mod2和表达式逻辑综合的高效程序
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212878
P. Besslich, M. Riege
{"title":"An efficient program for logic synthesis of mod-2 sum expressions","authors":"P. Besslich, M. Riege","doi":"10.1109/EUASIC.1991.212878","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212878","url":null,"abstract":"Resurrected interest in mod-2 sum logic requires efficient algorithms for synthesis of incompletely specified multiple-output functions. The authors report on a program based on new algorithms: Quasi-minimum covering is obtained in a polarized Reed-Muller domain using a modified disjoint sharp operator. Since a new algorithm for cubewise RMT is applied, and since no iterative procedures are employed, the program performs about an order of magnitude faster than other algorithms. The new program can handle functions of hundreds of variables on a personal computer. Solutions are (on average) superior to those of other methods.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"297 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120881990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A new method for the minimization of memory area in high level synthesis 一种高级合成中存储器面积最小化的新方法
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212869
B. Rouzeyre, G. Sagnes
{"title":"A new method for the minimization of memory area in high level synthesis","authors":"B. Rouzeyre, G. Sagnes","doi":"10.1109/EUASIC.1991.212869","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212869","url":null,"abstract":"Addresses the problem of register allocation and interconnect minimization during the high level synthesis of VLSI circuits, i.e. the problem of generating the minimum hardware to implement the intermediate values of a given behavioral description. The authors propose a method for simultaneously minimizing the whole area in relation with memory requirements, i.e. the number of registers, the number of related connections and associated control. This method is based on hierarchical clustering and performs global optimizations. Furthermore, the area costs of registers and connections are used as parameters, so that different styles of implementation can easily be taken into account and trade-offs between registers and connections can be made.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125811463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A genetic algorithm for the routing of VLSI circuits VLSI电路布线的遗传算法
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212864
M. Geraci, P. Orlando, F. Sorbello, G. Vassallo
{"title":"A genetic algorithm for the routing of VLSI circuits","authors":"M. Geraci, P. Orlando, F. Sorbello, G. Vassallo","doi":"10.1109/EUASIC.1991.212864","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212864","url":null,"abstract":"A channel and switch-box router based on an original and efficient optimization technique is presented. It uses modified Genetic Algorithms (GA) belonging to the family of Simulated Evolution. It combines the speed of Steepest Descent with the best features of GA, like the intrinsic high parallelism, the avoidance of local minima and an easy implementation. The algorithm can be applied both to channels and switchboxes and tests with several benchmarks have been performed; the results are qualitatively better or comparable to the most popular channel router.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126750965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信