A new method for the minimization of memory area in high level synthesis

Abstract

Addresses the problem of register allocation and interconnect minimization during the high level synthesis of VLSI circuits, i.e. the problem of generating the minimum hardware to implement the intermediate values of a given behavioral description. The authors propose a method for simultaneously minimizing the whole area in relation with memory requirements, i.e. the number of registers, the number of related connections and associated control. This method is based on hierarchical clustering and performs global optimizations. Furthermore, the area costs of registers and connections are used as parameters, so that different styles of implementation can easily be taken into account and trade-offs between registers and connections can be made.<>