{"title":"VLSI电路布线的遗传算法","authors":"M. Geraci, P. Orlando, F. Sorbello, G. Vassallo","doi":"10.1109/EUASIC.1991.212864","DOIUrl":null,"url":null,"abstract":"A channel and switch-box router based on an original and efficient optimization technique is presented. It uses modified Genetic Algorithms (GA) belonging to the family of Simulated Evolution. It combines the speed of Steepest Descent with the best features of GA, like the intrinsic high parallelism, the avoidance of local minima and an easy implementation. The algorithm can be applied both to channels and switchboxes and tests with several benchmarks have been performed; the results are qualitatively better or comparable to the most popular channel router.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"A genetic algorithm for the routing of VLSI circuits\",\"authors\":\"M. Geraci, P. Orlando, F. Sorbello, G. Vassallo\",\"doi\":\"10.1109/EUASIC.1991.212864\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A channel and switch-box router based on an original and efficient optimization technique is presented. It uses modified Genetic Algorithms (GA) belonging to the family of Simulated Evolution. It combines the speed of Steepest Descent with the best features of GA, like the intrinsic high parallelism, the avoidance of local minima and an easy implementation. The algorithm can be applied both to channels and switchboxes and tests with several benchmarks have been performed; the results are qualitatively better or comparable to the most popular channel router.<<ETX>>\",\"PeriodicalId\":118990,\"journal\":{\"name\":\"Euro ASIC '91\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Euro ASIC '91\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUASIC.1991.212864\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Euro ASIC '91","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUASIC.1991.212864","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A genetic algorithm for the routing of VLSI circuits
A channel and switch-box router based on an original and efficient optimization technique is presented. It uses modified Genetic Algorithms (GA) belonging to the family of Simulated Evolution. It combines the speed of Steepest Descent with the best features of GA, like the intrinsic high parallelism, the avoidance of local minima and an easy implementation. The algorithm can be applied both to channels and switchboxes and tests with several benchmarks have been performed; the results are qualitatively better or comparable to the most popular channel router.<>
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