{"title":"G2L:将低级几何设计转换为高级表示的系统","authors":"E. Pajarre, T. Ritoniemi, H. Tenhunen","doi":"10.1109/EUASIC.1991.212835","DOIUrl":null,"url":null,"abstract":"The author presents a methodology for converting VLSI design information from a geometry oriented database to a higher level database where electrical objects are the primitive elements. The conversion extracts the active elements and implicit connections from the geometry and recreates them using novel routing techniques producing geometrically identical layout. The methodology has been implemented in a GDS II to L language converter capable of converting databases containing whole chip designs. The system has been tested with processor designs and whole standard cell libraries.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"G2L: system for converting low-level geometrical designs to a higher level representation\",\"authors\":\"E. Pajarre, T. Ritoniemi, H. Tenhunen\",\"doi\":\"10.1109/EUASIC.1991.212835\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The author presents a methodology for converting VLSI design information from a geometry oriented database to a higher level database where electrical objects are the primitive elements. The conversion extracts the active elements and implicit connections from the geometry and recreates them using novel routing techniques producing geometrically identical layout. The methodology has been implemented in a GDS II to L language converter capable of converting databases containing whole chip designs. The system has been tested with processor designs and whole standard cell libraries.<<ETX>>\",\"PeriodicalId\":118990,\"journal\":{\"name\":\"Euro ASIC '91\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Euro ASIC '91\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUASIC.1991.212835\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Euro ASIC '91","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUASIC.1991.212835","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
G2L: system for converting low-level geometrical designs to a higher level representation
The author presents a methodology for converting VLSI design information from a geometry oriented database to a higher level database where electrical objects are the primitive elements. The conversion extracts the active elements and implicit connections from the geometry and recreates them using novel routing techniques producing geometrically identical layout. The methodology has been implemented in a GDS II to L language converter capable of converting databases containing whole chip designs. The system has been tested with processor designs and whole standard cell libraries.<>