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High speed CMOS operational amplifier 高速CMOS运算放大器
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212847
S. Schwehr, T. Fuchs, K. Dzahini, B. Boutherin, M. Le Helley
{"title":"High speed CMOS operational amplifier","authors":"S. Schwehr, T. Fuchs, K. Dzahini, B. Boutherin, M. Le Helley","doi":"10.1109/EUASIC.1991.212847","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212847","url":null,"abstract":"In this paper authors present a new approach to fast CMOS opamp design. This approach benefits from the advantages offered by full complementary implementations of well known subcircuits, to enhance the speed of such an operational amplifier and to better organize and economize layout generation. Since the consequent structured topology of full complementary circuits like the present opamp is well suited to a cell based design, simulation time and layout generation time could have been decreased by a factor of almost five. This results in an opamp which exhibits a slew-rate of 800 V/ mu s (for a positive input step) and whose mask layout was done in three days.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"138 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132227926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A double-sourced ASIC for contactless badges 用于非接触式徽章的双源ASIC
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212880
R. Petigny, P. Cabon
{"title":"A double-sourced ASIC for contactless badges","authors":"R. Petigny, P. Cabon","doi":"10.1109/EUASIC.1991.212880","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212880","url":null,"abstract":"Design of the same circuit with two different technology sources for an identification badge is presented. In the first source, a CMOS 3 mu m N-well technology issued with an area of 6 mm/sup 2/ (9300 sq mils), in the second source, a CMOS 2 mu m N-well technology is used for an area of 4 mm/sup 2/ (6200 sq mils). The power supply consists in a 3 V lithium battery. Design for the second source is mostly realized through CAD processing of the first circuit GDS2 file.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134576573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI implementation of a cochlear model 一个人工耳蜗模型的VLSI实现
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212896
N. Avellana, F. Garrido, J. Carrabina, E. Valderrama, P. Gómez
{"title":"VLSI implementation of a cochlear model","authors":"N. Avellana, F. Garrido, J. Carrabina, E. Valderrama, P. Gómez","doi":"10.1109/EUASIC.1991.212896","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212896","url":null,"abstract":"In this model, the human cochlea is divided into six equal sections; the acoustic wave is studied in one section. The aim of the circuit is an implementation of the equations from the model. In order to make all the necessary operations, the arithmetic unit is able to do products, additions and transferences between registers and memories.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114533454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A data-flow processor for real-time low-level image processing 用于实时低级图像处理的数据流处理器
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212887
G. Quénot, B. Zavidovique
{"title":"A data-flow processor for real-time low-level image processing","authors":"G. Quénot, B. Zavidovique","doi":"10.1109/EUASIC.1991.212887","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212887","url":null,"abstract":"A chip featuring two coupled data-flow processors (DFPs) has been designed. It is to be mesh-connected into large processor arrays dedicated primarily to image processing. Each processor operates on 25 MBytes/s data-flows and performs up to 50 million 8- or 16-bit arithmetic operations per second. The chip has been processed in a 1 mu m CMOS technology. It includes 160000 transistors in a 84 mm/sup 2/ die size area, its clock is at 25 MHz and it is packaged in a 144-pin PGA package. Computations are performed on the fly on a data-flow that comes from a digital video camera. One physical operator is associated to each operation involved in the algorithm. An experimental data-flow system including eight processors in a 2*2*2 3D network has been built. Edge detection, row sums, column sums and histograms have been implemented on it at digital video speed.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123576433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Optimal module orientation by block rotation and wire length minimisation 通过块旋转和导线长度最小化来优化模块方向
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212862
P. Drenth, J. van Gisbergen, M. Lousberg
{"title":"Optimal module orientation by block rotation and wire length minimisation","authors":"P. Drenth, J. van Gisbergen, M. Lousberg","doi":"10.1109/EUASIC.1991.212862","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212862","url":null,"abstract":"There are two objectives for optimal module orientation: minimisation of the amount of unused area and of the wire lengths. For the first problem a bottom-up block combining algorithm is used, adapted from a floorplanning algorithm. For the second objective an adaptation of an analytical method is used. The adaptation results in a significant reduction in computation requirements. The authors combined both methods and achieved good results.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126068116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of a robust analog/digital ASIC interface for hard industrial environment 一种适用于硬工业环境的模拟/数字ASIC接口设计
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212840
J. Suutari, H. Tenhunen, J. Nikula
{"title":"Design of a robust analog/digital ASIC interface for hard industrial environment","authors":"J. Suutari, H. Tenhunen, J. Nikula","doi":"10.1109/EUASIC.1991.212840","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212840","url":null,"abstract":"The industrial environment places hard requirements on the analog structures of a current monitoring unit. An ASIC circuit is a good solution to gaining robust electronics for the harsh environment. In this paper an analog structure of a current monitoring unit is presented which can be used in several different applications such as measuring various kinds of apparatus. A prototype mixed analog/digital BiCMOS ASIC was designed and implemented using both the standard cells from the ASIC vendor and full custom blocks. Extra measures in design were put into effect for circuit robustness.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124567981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI-oriented asynchronous controller synthesis based on a flip-flop cell array structure 基于触发器单元阵列结构的面向vlsi异步控制器合成
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212882
K. Cho, M. Ikeda, K. Asada
{"title":"VLSI-oriented asynchronous controller synthesis based on a flip-flop cell array structure","authors":"K. Cho, M. Ikeda, K. Asada","doi":"10.1109/EUASIC.1991.212882","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212882","url":null,"abstract":"Presents a new implementation method of asynchronous controllers based on a cell array structure. Two kinds of cells are used to map asynchronous circuits synthesized by one-hot code assignment into layout; a basic cell with a flip-flop memory and set-reset logic, and an extension cell with set-reset logic. The present method gives considerable area reduction compared with a PLA-like implementation.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121659051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of a linear array element for matrix multiplication 实现了一个线性数组元素的矩阵乘法
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212861
M. Morante, L. Saiz de Quevedo, P. Tabuenca, J.I. Martinez, E. Villar
{"title":"Implementation of a linear array element for matrix multiplication","authors":"M. Morante, L. Saiz de Quevedo, P. Tabuenca, J.I. Martinez, E. Villar","doi":"10.1109/EUASIC.1991.212861","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212861","url":null,"abstract":"The implementation of a linear array element for matrix multiplication is described. The cell corresponds to the fully pipelined model. First, its architecture and floorplan are described. Secondly, the design process is completed. Third, its area and time performances are analyzed and finally, the testing of the chips is carried out.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122834466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new graph theoretical approach to the selection of rip-ups 一个新的图论方法来选择撕裂
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212863
M. Bartholomeus, M. Raith
{"title":"A new graph theoretical approach to the selection of rip-ups","authors":"M. Bartholomeus, M. Raith","doi":"10.1109/EUASIC.1991.212863","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212863","url":null,"abstract":"Presents a new approach to the selection of rip-ups to be used in a rip-up and reroute router. This technique is based on a hypergraph model. The novelty of the authors' approach is that given a blocking situation, a minimal set of connections to be ripped-up is simultaneously calculated and removed. The selection of the best ripping set is based on its reroutability potential.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114935226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A dedicated circuit for real time motion estimation 用于实时运动估计的专用电路
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212886
O. Colavin, A. Artieri, J. Naviner, R. Pacalet
{"title":"A dedicated circuit for real time motion estimation","authors":"O. Colavin, A. Artieri, J. Naviner, R. Pacalet","doi":"10.1109/EUASIC.1991.212886","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212886","url":null,"abstract":"Presents a circuit dedicated to real-time motion estimation in video compression systems. It computes motion vectors in the range -8/+7 for 8*4n and 16*4n sized blocks at pixel rates up to 18 MHz. The architecture is based on a 128 processor systolic array. This 270000 transistor IC uses a two metal layer 1.2 mu m CMOS process.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134063981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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