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A good input ordering for circuit verification based on binary decision diagrams 基于二元决策图的电路验证的良好输入顺序
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212832
G. Saucier, F. Poirot
{"title":"A good input ordering for circuit verification based on binary decision diagrams","authors":"G. Saucier, F. Poirot","doi":"10.1109/EUASIC.1991.212832","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212832","url":null,"abstract":"Verification methods for standard cell logic are based on binary decision diagrams (BDD) comparison. The reference Boolean equations as well as the network of standard cell logic are represented by ordered BDDs (OBDDs). The main issue is to find a good input ordering to reduce both the number of nodes in the BDDs and the computation time needed to construct as well as to compare them.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122630848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Test generation using cross-observability calculations 使用交叉可观察性计算生成测试
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212853
E. Cerny, E. Aboulhamid, C. Mauras, P. Rioux
{"title":"Test generation using cross-observability calculations","authors":"E. Cerny, E. Aboulhamid, C. Mauras, P. Rioux","doi":"10.1109/EUASIC.1991.212853","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212853","url":null,"abstract":"The authors propose a symbolic algorithm for test generation of combinational circuits based on a sweep from the outputs to the inputs that calculates the relation between the values on the lines cut by this sweep along the way. The algorithm may generate the entire set of test vectors for a particular fault, or only a subset of this set, as required. A simple Boolean version of the algorithm is introduced to generate tests under the stuck-at-0/stuck-at-1 model and then a more complex version using multivalued logic is presented for generating tests for stuck-open faults in CMOS circuits.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125844904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ACC: automatic cell characterization
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212866
K. Anshumali
{"title":"ACC: automatic cell characterization","authors":"K. Anshumali","doi":"10.1109/EUASIC.1991.212866","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212866","url":null,"abstract":"The advent of aggressive submicron-VLSI technologies requires an accompanying development in characterization-tools. The large number and diversity of library-components and their multidimensional parameters makes it imperative to employ a fast and automatic flow embodying rigorous methodologies to accomplish the task of library-characterization. This paper describes the ACC (Automatic Cell Characterization) system which combines generic operation, fast electrical simulation and numerical analysis to automatically characterize a library in a multidimensional manner.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126064404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An ASIC for image dilation and erosion 用于图像膨胀和侵蚀的ASIC
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212857
M. Baatour, J. Rampon, Y. Tertre
{"title":"An ASIC for image dilation and erosion","authors":"M. Baatour, J. Rampon, Y. Tertre","doi":"10.1109/EUASIC.1991.212857","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212857","url":null,"abstract":"A VLSI chip to compute two morphological operations, dilation and erosion, over discrete black and white images is presented here. The chip contains 96 PEs organized as a 12*8 2D array of processing elements (PEs) performing in an SIMD mode. Each PE is connected to its four neighbors.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133439767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flexible datapath compilation for Phideo 灵活的数据路径编译的Phideo
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212870
A. van der Werf, B. McSweeney, J. van Meerbergen, P. Lippens, W. Verhaegh
{"title":"Flexible datapath compilation for Phideo","authors":"A. van der Werf, B. McSweeney, J. van Meerbergen, P. Lippens, W. Verhaegh","doi":"10.1109/EUASIC.1991.212870","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212870","url":null,"abstract":"Discusses design techniques for datapaths for video applications. Currently, PHIDEO, a silicon compiler for high speed algorithms, is being developed at the Philips Research Laboratories as part of SPRITE. Datapath compilation is one of the subtasks of this compiler. It will be shown that by including optimization tools like retiming, logic synthesis, and placement & routing the generators are less parametrized. Thereby the datapath compiler becomes more flexible.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"477 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129344352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
6 bits programmable VHF amplifier 6位可编程VHF放大器
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212848
C. Vanhecke
{"title":"6 bits programmable VHF amplifier","authors":"C. Vanhecke","doi":"10.1109/EUASIC.1991.212848","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212848","url":null,"abstract":"The author describes the design of an analog ASIC to be used for amplification applications in the field of spatial telecommunications. It was produced using an HF2C bipolar technology developed by the French company Thomson TMS. The amplifier was designed as part of an equipment feasibility study for Alcatel Espace. The author discusses the input stage, variable gain stage, voltage regulator and layout.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123498290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Using a CMOS ASIC technology for the development of an integrated ISFET sensor 采用CMOS ASIC技术开发了集成的ISFET传感器
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212837
K. Dzahini, F. Gaffiot, M. Le Helley
{"title":"Using a CMOS ASIC technology for the development of an integrated ISFET sensor","authors":"K. Dzahini, F. Gaffiot, M. Le Helley","doi":"10.1109/EUASIC.1991.212837","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212837","url":null,"abstract":"To take advantage of microelectronics, attempts have been made to integrate sensors in silicon and furthermore to accommodate the whole system formed of the sensor and its signal processing circuit. The major problem is the compatibility between both processes: elaboration of the sensor and integration of the measurement circuit. In this paper the authors present a method allowing industrial production of integrated ISFET sensor. An ASIC CMOS line is used to integrate the signal processing circuit; then the sensor is fabricated by a specific process that does not alter the function of the circuit.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121728418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ASIC cryptographical processor based on DES 基于DES的ASIC加密处理器
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212850
I. Verbauwhede, F. Hoornaert, J. Vandewalle, H. de Man
{"title":"ASIC cryptographical processor based on DES","authors":"I. Verbauwhede, F. Hoornaert, J. Vandewalle, H. de Man","doi":"10.1109/EUASIC.1991.212850","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212850","url":null,"abstract":"To date, many commercial applications in telecommunications, data transmission and data storage require a high level of cryptographical protection. The ASIC processor, presented here, can be programmed to execute a large set of cryptographical functions, not found in other cryptographical devices. Novel architectures for both data path and controller have been designed to realize this high degree of programmability, while still reaching a high throughput. The compact processor counts 18 K transistors on 25 mm/sup 2/ in a 2.4 mu m CMOS process and yet it reaches a throughput of 30 Mbit/s for every single-encryption mode. It is the fastest data encryption standard (DES) processor currently available.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121322801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Datapath layout generation with in-the-cell routing and optimal column resequencing 数据路径布局生成与单元内路由和最优列重排序
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212834
P. Drenth, C. Strolenberg
{"title":"Datapath layout generation with in-the-cell routing and optimal column resequencing","authors":"P. Drenth, C. Strolenberg","doi":"10.1109/EUASIC.1991.212834","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212834","url":null,"abstract":"The authors describe a new layout style for datapath circuits. Novel features of their datapath layout style are the use of a routing channel inside the bitslice cells and leaving the designer full freedom to define the interconnections between datapath columns, instead of imposing a fixed bus architecture. irregular datapaths are permitted and can be incorporated easily. The columns of the datapath are resequenced such that routing costs are minimal.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121738589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Testing ASICs at-speed 快速测试asic
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212843
C. Gauthron
{"title":"Testing ASICs at-speed","authors":"C. Gauthron","doi":"10.1109/EUASIC.1991.212843","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212843","url":null,"abstract":"At-speed test of ASICs is effective to detect delay faults, however, strobing is difficult because of process variations. In this paper two methodologies to generate at-speed test vectors are described. One is based on the comparison and merger of simulation traces obtained with different timing conditions. The other is a two-pass test approach.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122143014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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