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Test generation of controllers using the synthesis specifications 使用综合规范测试控制器的生成
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212851
M. Karam, G. Saucier, C. Jay
{"title":"Test generation of controllers using the synthesis specifications","authors":"M. Karam, G. Saucier, C. Jay","doi":"10.1109/EUASIC.1991.212851","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212851","url":null,"abstract":"The test generation of finite state machines proposed by the authors is performed by going first through all the transitions of the control flowgraph them completing the test set of the undetected faults using the Poage method. In more detail the mixed test generation method starts with a functional test generation method producing a very short and effective (in terms of detection quality) test sequence. An original input don't care optimization phase is invoked. A second phase is based upon a deterministic approach to reach 100% coverage still using the finite state machine specifications.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122576685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High precision SPICE models for the simulation of analogue CMOS circuits 用于模拟CMOS电路仿真的高精度SPICE模型
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212868
B. Ankele, F. Schrank
{"title":"High precision SPICE models for the simulation of analogue CMOS circuits","authors":"B. Ankele, F. Schrank","doi":"10.1109/EUASIC.1991.212868","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212868","url":null,"abstract":"Enhanced SPICE models are developed for the simulation of analogue CMOS circuits. The well resistor model describes the voltage, geometry and temperature dependence of the resistance which is crucial for the characterization of a bandgap reference circuit. The single-operating-region MOS model uses electrically effective voltages for increased accuracy and continuity of the derivatives. It forms the basis of the lateral bipolar transistor model which includes the simulation of the MOS-to-bipolar transition region for optional gate voltages.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129697136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A temperature and voltage measurement cell for VLSI circuits 用于VLSI电路的温度和电压测量单元
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212842
G. Quénot, N. Paris, B. Zavidovique
{"title":"A temperature and voltage measurement cell for VLSI circuits","authors":"G. Quénot, N. Paris, B. Zavidovique","doi":"10.1109/EUASIC.1991.212842","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212842","url":null,"abstract":"A temperature and voltage measurement cell (TVM cell) for VLSI circuits has been developed. It requires less than 1 mm/sup 2/ of core area (for a 2 mu m CMOS technology) and only 4 I/O pins. It can be integrated into any GMOS VLSI circuit, permitting the measurement of the circuit die temperature (T) and its core power supply voltage (V) while the chip is operated normally in a system. It achieves simultaneously an accuracy better than 50 mV and 3 degrees C. Output values are averages of the parameter values during a 1 ms period.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129165913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 70
Real time image processing system: design of an area CCD sensor driving integrated circuit 实时图像处理系统:一种面积CCD传感器驱动集成电路的设计
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212856
E. Fauvet, M. Paindavoine, J.-F. Kirilenko, M. Robert, D. Deschacht, D. Auvergne
{"title":"Real time image processing system: design of an area CCD sensor driving integrated circuit","authors":"E. Fauvet, M. Paindavoine, J.-F. Kirilenko, M. Robert, D. Deschacht, D. Auvergne","doi":"10.1109/EUASIC.1991.212856","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212856","url":null,"abstract":"Presents the design of an integrated clock generation device which can drive an area CCD sensor used in a fast image system. The authors describe the circuit specification, the architecture of the ASIC designed in a 2 mu m CMOS technology with the ES2 Solo 1400 design tool.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116262249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 16/24-bit DSP-ASIC coprocessor for AC motor modelling 用于交流电机建模的16/24位DSP-ASIC协处理器
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212894
S. Ovaska, O. Vainio, J. Pasanen
{"title":"A 16/24-bit DSP-ASIC coprocessor for AC motor modelling","authors":"S. Ovaska, O. Vainio, J. Pasanen","doi":"10.1109/EUASIC.1991.212894","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212894","url":null,"abstract":"A discrete-time computational AC motor model is derived and analyzed for the purpose of advanced motor control. The starting point is a continuous-time model defined by a pair of simultaneous complex-coefficient differential equations. The discrete-time model is derived using the forward-difference (FD) approximation. The exact dependence between stability and the minimum sampling rate in the FD approach is shown. An efficient implementation architecture is given, based on DSP techniques. A 16/24-bit DSP-ASIC coprocessor prototype implementing the AC motor model is introduced.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127094763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A SIMD machine for beamforming on a chip 在芯片上进行波束形成的SIMD机器
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212897
J. Giacalone, Y. Del Gallo
{"title":"A SIMD machine for beamforming on a chip","authors":"J. Giacalone, Y. Del Gallo","doi":"10.1109/EUASIC.1991.212897","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212897","url":null,"abstract":"A CMOS integrated circuit containing 400000 transistors was produced to implement a beamforming algorithm. Using an SIMD architecture, it implements two pipelined 24-bits floating point multiply-accumulate units, developing a total computing power of 64 Mflops for a 60-ns cycle time. This circuit is controlled by a micro-sequencer which manages an external memory of two Mwords (24-bits instructions and data), simultaneously accessing four data elements. Designed for use in a parallel machine environment, it has a built-in communication manager.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133281447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automatic synthesis of Boolean functions on Xilinx and Actel programmable devices 在Xilinx和Actel可编程设备上自动合成布尔函数
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212877
P. Sicard, M. Crastes, K. Sakouti, G. Saucier
{"title":"Automatic synthesis of Boolean functions on Xilinx and Actel programmable devices","authors":"P. Sicard, M. Crastes, K. Sakouti, G. Saucier","doi":"10.1109/EUASIC.1991.212877","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212877","url":null,"abstract":"Synthesis methods for two types of programmable devices Xilinx and Actel are presented. The optimization criterion is first the critical path of the final circuit and secondly the number of devices required to implement the function. The methods consist of an adequate factorization step followed by a mapping adapted to each target.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127618713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
An image decoding ASIC for space-based applications 一种用于天基应用的图像解码专用集成电路
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212888
D. B. Kasle, G. Demicheli
{"title":"An image decoding ASIC for space-based applications","authors":"D. B. Kasle, G. Demicheli","doi":"10.1109/EUASIC.1991.212888","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212888","url":null,"abstract":"The multi-anode microchannel array (MAMA) is a photon counting detector with primarily astronomical applications which decodes the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the anode array. A space-based realization of the MAMA detector requires that the decoding circuit be an application specific integrated circuit because of power, size and weight constraints. A 1.5 micron CMOS gate array version of the decoder has been fabricated and tested. The chip's development and characteristics are presented, and the ASIC decoder is contrasted with existing discrete component decoders in terms of size, speed, power, reliability, and operational flexibility. A new algorithm incorporated into the ASIC decoder which doubles the pixel spatial resolution is also described.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115733310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
VLSI design of an 8-bit fixed point CORDIC processor with extended operation set 具有扩展运算集的8位定点CORDIC处理器的VLSI设计
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212874
D. Metafas, G. Krikis, C. Goutis
{"title":"VLSI design of an 8-bit fixed point CORDIC processor with extended operation set","authors":"D. Metafas, G. Krikis, C. Goutis","doi":"10.1109/EUASIC.1991.212874","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212874","url":null,"abstract":"An architecture of a DSP fixed point, pipelined processor is presented. It provides a single hardware structure with a full set of elementary arithmetic operations which include circular and hyperbolic functions, square root, logarithm as well as multiplication and division. Its powerful functionality makes it an ideal processing element in high speed multiprocessor applications. The processor architecture is based on the CORDIC and CCM algorithms and it is fully parallel and pipelined. An 8-bit fixed point chip has been designed using the VENUS-S semicustom design system in CMOS 1.5 mu m technology.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116507792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
DBIMOS: the mix in one approach DBIMOS:一种方法的混合
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212903
E. Teck
{"title":"DBIMOS: the mix in one approach","authors":"E. Teck","doi":"10.1109/EUASIC.1991.212903","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212903","url":null,"abstract":"The DBIMOS technology is a major step forward towards system integration. The 100 V DBIMOS, 40 V bipolar and 18 V CMOS transistors allow the smart interface market to be served. This market demands high performance analog functions, advanced signal processing, logic circuitry and high voltage and high current drivers to be combined on a cell-based ASIC. The target market, the technology, cell library and a typical application are presented.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116596331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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