{"title":"在芯片上进行波束形成的SIMD机器","authors":"J. Giacalone, Y. Del Gallo","doi":"10.1109/EUASIC.1991.212897","DOIUrl":null,"url":null,"abstract":"A CMOS integrated circuit containing 400000 transistors was produced to implement a beamforming algorithm. Using an SIMD architecture, it implements two pipelined 24-bits floating point multiply-accumulate units, developing a total computing power of 64 Mflops for a 60-ns cycle time. This circuit is controlled by a micro-sequencer which manages an external memory of two Mwords (24-bits instructions and data), simultaneously accessing four data elements. Designed for use in a parallel machine environment, it has a built-in communication manager.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"196 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A SIMD machine for beamforming on a chip\",\"authors\":\"J. Giacalone, Y. Del Gallo\",\"doi\":\"10.1109/EUASIC.1991.212897\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS integrated circuit containing 400000 transistors was produced to implement a beamforming algorithm. Using an SIMD architecture, it implements two pipelined 24-bits floating point multiply-accumulate units, developing a total computing power of 64 Mflops for a 60-ns cycle time. This circuit is controlled by a micro-sequencer which manages an external memory of two Mwords (24-bits instructions and data), simultaneously accessing four data elements. Designed for use in a parallel machine environment, it has a built-in communication manager.<<ETX>>\",\"PeriodicalId\":118990,\"journal\":{\"name\":\"Euro ASIC '91\",\"volume\":\"196 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Euro ASIC '91\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUASIC.1991.212897\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Euro ASIC '91","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUASIC.1991.212897","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CMOS integrated circuit containing 400000 transistors was produced to implement a beamforming algorithm. Using an SIMD architecture, it implements two pipelined 24-bits floating point multiply-accumulate units, developing a total computing power of 64 Mflops for a 60-ns cycle time. This circuit is controlled by a micro-sequencer which manages an external memory of two Mwords (24-bits instructions and data), simultaneously accessing four data elements. Designed for use in a parallel machine environment, it has a built-in communication manager.<>
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