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An A/D-chip for accurate power measurement A/ d芯片用于精确的功率测量
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212838
R. Rauscher, V. Grupe
{"title":"An A/D-chip for accurate power measurement","authors":"R. Rauscher, V. Grupe","doi":"10.1109/EUASIC.1991.212838","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212838","url":null,"abstract":"The authors describe the development of an integrated circuit. Starting with the specification and the knowledge of usual mathematical procedures the design procedure is discussed. The intention is to support high speed accurate measurement of voltage and current including simultaneous calculations of RMS (root mean square) of voltage and current as well as effective power for arbitrary periodic AC signals. The chip was designed using a 1.5 mu m CMOS process.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122960798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
VHDL in logic synthesis-an applications perspective VHDL在逻辑合成中的应用前景
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212889
W. Ries, K. M. Just
{"title":"VHDL in logic synthesis-an applications perspective","authors":"W. Ries, K. M. Just","doi":"10.1109/EUASIC.1991.212889","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212889","url":null,"abstract":"Shows some aspects of VHDL for synthesis (and simulation) from a very practical view. One of the aspects addressed is the integration of VHDL into current design flows with respect to the need of graphical interfaces. A synthesis example shows the advantage of VHDL to facilitate the specification of the structure of a block's architecture together with its functional description. Comparisons to other means of circuit specification show its expressiveness to cover all practical applications. This gives an estimation of the necessary efforts to port already existing circuit models into VHDL.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123328094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advances in high speed ECL technology and interconnection techniques 高速ECL技术和互连技术的进展
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212904
K. Ohno
{"title":"Advances in high speed ECL technology and interconnection techniques","authors":"K. Ohno","doi":"10.1109/EUASIC.1991.212904","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212904","url":null,"abstract":"Explores recent developments in bipolar silicon technology and the production of advanced ECL (Emitter Coupled Logic) IC devices. Refined structural techniques and device scaling have been the major contributors to improved performance. Examples are given of how these silicon techniques have been combined with high density packaging and used to implement today's 'super computers'. The effect of reduced basic gate delays and on-chip wiring delays is contrasted with the effect of relatively long interconnection delays on the whole system performance. Further developments aimed at improving both basic gate delay and wiring delay are continuing, and even higher performance bipolar silicon devices will continue.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114191177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A smart power IC for high side driver applications 一种用于高侧驱动应用的智能功率IC
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212900
Y. Droinet
{"title":"A smart power IC for high side driver applications","authors":"Y. Droinet","doi":"10.1109/EUASIC.1991.212900","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212900","url":null,"abstract":"New technologies allow the realization of power MOSFET, bipolar transistors and complex analog and digital structures on the same piece of silicon. A high side switch IC for current and high voltage applications is presented. This smart power chip is optimized to drive inductive and resistive loads in an automotive environment. The chip contains fault diagnostics to detect any failure at system level. This paper also presents the new power BICMOS technology used for this design.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127636757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Digital speed regulation for a washing machine motor 用于洗衣机电机的数字调速
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212841
C. Ferrer, J. M. Aguirre
{"title":"Digital speed regulation for a washing machine motor","authors":"C. Ferrer, J. M. Aguirre","doi":"10.1109/EUASIC.1991.212841","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212841","url":null,"abstract":"In this paper a semicustom circuit is presented for the digital regulation of the speed of a washing machine motor. This is a good example of a circuit in which the consideration of high-level synthesis and testability criteria enables an ASIC to be designed with little effort.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129011663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-quality physical designs of CMOS ICs CMOS集成电路的高质量物理设计
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212846
J. Sousa, F. Gonçalves, J. P. Teixeira
{"title":"High-quality physical designs of CMOS ICs","authors":"J. Sousa, F. Gonçalves, J. P. Teixeira","doi":"10.1109/EUASIC.1991.212846","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212846","url":null,"abstract":"The authors describe a methodology for the assessment and enhancement of the physical testability of CMOS digital ICs, and to present a set of testability design rules to avoid 'difficult to detect' faults, especially open faults. The methodology and the design rules are used in the development of a high-quality, highly testable cell library. A design example is presented, which ascertains the usefulness of the approach, and the achievable gains in testability, reliability and eventually in yield.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130367794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
VLSI ASIC design for MAC video processing integration in SGS-Thomson microelectronics chip set 用于MAC视频处理的VLSI ASIC设计集成在sgs -汤姆逊微电子芯片组中
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212879
A. Lorenzi, V. Verfaillie, G. Vanneuville, N. Chaumartin, G. Gerot, J.M. Troude
{"title":"VLSI ASIC design for MAC video processing integration in SGS-Thomson microelectronics chip set","authors":"A. Lorenzi, V. Verfaillie, G. Vanneuville, N. Chaumartin, G. Gerot, J.M. Troude","doi":"10.1109/EUASIC.1991.212879","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212879","url":null,"abstract":"The paper shows how the methodology of design and the CAD solution are important in the development of VLSI circuits. The system maker know-how also appears very important and must be associated with a full custom approach. The authors describe the different development steps mainly from the design methodology point of view. As HDMAC is chosen to be the future European HDTV standard, this chip-set must follow the compatibility between the MAC standard and the HDMAC. SGS-Thomson has developed advanced technologies in CMOS and BICMOS which can easily migrate towards denser ones without any significant changes of the ICs. For these reasons, SGS-Thomson has undertaken the development of a chip-set composed of three dedicated ICs for MAC decoders: acquisition circuit TV3810, video processing circuit TV3820, and data processing circuit TV3830.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132197369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of highly reliable VLSI processors incorporating concurrent error detection/correction 采用并发错误检测/校正的高可靠VLSI处理器的设计
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212845
G. Russell, I. Elliott
{"title":"Design of highly reliable VLSI processors incorporating concurrent error detection/correction","authors":"G. Russell, I. Elliott","doi":"10.1109/EUASIC.1991.212845","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212845","url":null,"abstract":"The full exploitation of the benefits to be gained by the high packing densities achievable by present day fabrication technologies for VLSI circuits, is overshadowed to some extent by the increase in the susceptibility of the small geometry circuits to intermittent faults. Unfortunately, standard testing strategies cannot detect these types of faults. The increased use of VLSI circuits in 'safety-critical' applications has necessitated the incorporation of concurrent error detection/correction mechanisms into VLSI circuits to continuously monitor the operation of the circuit to detect and, in some cases subsequently correct these faults. The author describes the implementation of two schemes for concurrent error detection/correction in VLSI processors.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133799964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Algorithmic ADC for use in ASIC design 用于ASIC设计的算法ADC
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212899
K. Deevy
{"title":"Algorithmic ADC for use in ASIC design","authors":"K. Deevy","doi":"10.1109/EUASIC.1991.212899","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212899","url":null,"abstract":"An algorithmic analog to digital converter is described which combines a fast conversion time of less than 300 ns with a small circuit area of 0.8 mm/sup 2/. The circuit operates from a+5 V power supply and is ideally suited for use as a general purpose cell in analogue and mixed signal ASIC design. The ADC operates in current mode and an accurate current sensing technique allows the comparators to operate very quickly even in the presence of small signal differences. The current mode approach has the advantage of small signal voltage swings, low node capacitance and therefore fast operation. The resolution of the converter is 8-bits as this will satisfy the requirements of many applications including digital mobile radio and disk drive servo control chips. Results are presented for a prototype chip fabricated on a 2- mu m BiCMOS process.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114139767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of VLSI layout style implementations for efficiency VLSI布局风格实现的效率评估
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212836
M. Robert, J. Trauchessec, G. Cathébras, V. Bonzom, N. Azémard, D. Deschacht, D. Auvergne
{"title":"Evaluation of VLSI layout style implementations for efficiency","authors":"M. Robert, J. Trauchessec, G. Cathébras, V. Bonzom, N. Azémard, D. Deschacht, D. Auvergne","doi":"10.1109/EUASIC.1991.212836","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212836","url":null,"abstract":"As an attempt to define a priori mapping rules for performance driven layout, the authors show in this paper how an automatic module generator can be used to compare different implementation styles of regular layout. Speed and area performances of gate and linear matrix approaches are compared. It is clearly shown that abutment of diffusions results in lower 'locox' parasitic capacitances inducing higher speed performances for linear matrix style.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126246659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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