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A versatile building-block for high-speed current-mode analog ICs 用于高速电流模式模拟ic的通用构建块
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212902
R. Steck, A. Kostka, K. Lehmann
{"title":"A versatile building-block for high-speed current-mode analog ICs","authors":"R. Steck, A. Kostka, K. Lehmann","doi":"10.1109/EUASIC.1991.212902","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212902","url":null,"abstract":"A complementary transconductance stage is presented that can be employed as a versatile building block for current-mode as well as for voltage-mode applications. Starting from the basic topology, the authors discuss design techniques for DC-offset compensation and present a boosting circuit that results in dramatic improvements in the large-signal characteristics of the circuit. A realisation of the proposed structure using the CBICU-technology of AT&T Microelectronics features excellent dynamic characteristics with virtually no slew rate limitations. A discussion on typical application circuits concludes the paper.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115601132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Synthesis and partitioning of standard cells for floorplan optimization 平面图优化标准单元的合成和划分
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212883
E. Chotin, T. Besson, G. Saucier
{"title":"Synthesis and partitioning of standard cells for floorplan optimization","authors":"E. Chotin, T. Besson, G. Saucier","doi":"10.1109/EUASIC.1991.212883","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212883","url":null,"abstract":"Glue logic of standard cells is partitioned into subsets to fill holes in a floorplan. This partitioning is driven by input constraints as the logic put in a hole has to depend on the inputs on the border of this hole. It has also to respect area ratio. The partitioning presented is prepared during factorization to allow an effective partitioning in terms of minimization of the crossing wires. This input driven partitioning method for Boolean networks consists of an adequate factorization step followed by a partitioning of factorized trees. The first step allows one to obtain easily partitionable trees for the partitioning algorithm.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125310156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and implementation of a dedicated neural network for handwritten digit recognition 手写体数字识别专用神经网络的设计与实现
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212892
P. Alla, L. Masse-Navette, J. Ouali, G. Saucier, S. Knerr, L. Personnaz, G. Dreyfus
{"title":"Design and implementation of a dedicated neural network for handwritten digit recognition","authors":"P. Alla, L. Masse-Navette, J. Ouali, G. Saucier, S. Knerr, L. Personnaz, G. Dreyfus","doi":"10.1109/EUASIC.1991.212892","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212892","url":null,"abstract":"The automatic recognition of handwritten digits seems to be one of the most promising fields for applications of artificial neural networks; various studies have shown that good recognition rates can be obtained on large 'real-world' data bases. This paper presents: (i) the design of a network architecture, resulting from a stepwise procedure developed at ESPCI for simultaneously building and training a neural network, intended for the automatic recognition of isolated handwritten digits and (ii) a silicon implementation of that network, using a general-purpose neural circuit architecture developed at CSI.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116085238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
DSP-ASIC based voltage feedback switching regulator chip for electromechanical contactor 基于DSP-ASIC的机电接触器电压反馈开关调节芯片
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212901
P. Solanti, T. Karema, H. Tenhunen
{"title":"DSP-ASIC based voltage feedback switching regulator chip for electromechanical contactor","authors":"P. Solanti, T. Karema, H. Tenhunen","doi":"10.1109/EUASIC.1991.212901","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212901","url":null,"abstract":"Industrial power control systems are developed rapidly toward more complex and highly integrated systems. One of the main switching components, an electromechanical contactor, has remained basically the same during the last 20 years. An electronic control device, described in this paper, improves the contactor stability and offers new features to the design of the motor control center. The heart of the control device is a digital, voltage controlled switching regulator, limiting the coil current to a safe value in the voltage range, which is three times the nominal voltage of the controlled coil. In the digital solution, the benefits of robust digital filter and PWM structures and Sigma Delta A/D-converter are combined to create a very small size control ASIC, which is able to operate in a noisy environment and to control reliably a nonlinear inductive load.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116891430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a complex combinational ASIC with educational aims 以教育为目的的复杂组合专用集成电路的设计
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212860
P. Amblard, M. Hollett, S. Audie, E. Bittar, C. Chaudy, P. Coulomb, S. Le Men, O. Ondoa, E. Piot, F. Pogodalla
{"title":"Design of a complex combinational ASIC with educational aims","authors":"P. Amblard, M. Hollett, S. Audie, E. Bittar, C. Chaudy, P. Coulomb, S. Le Men, O. Ondoa, E. Piot, F. Pogodalla","doi":"10.1109/EUASIC.1991.212860","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212860","url":null,"abstract":"Presents complex combinational ASIC design by 4th year computer science students. The circuit, combinational, is complex enough to exhibit several problems. It performs calendar-type calculations. The parts of the circuit are presented. The challenge was to design and test such a circuit during one academic year. The steps are explained.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125381817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ASIC design considerations for power management in laptop computers 笔记本电脑电源管理的ASIC设计注意事项
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212839
Y.A. Dubois, J. J. Farrell
{"title":"ASIC design considerations for power management in laptop computers","authors":"Y.A. Dubois, J. J. Farrell","doi":"10.1109/EUASIC.1991.212839","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212839","url":null,"abstract":"During battery operation, the laptop personal computer system power management is an extremely critical design criteria. A device that controls power at differing levels-in the keyboard, the display, as well as in the system's integrated circuits themselves-is described in this paper. Automatic system turn-on, wake up sequencing, low batter indication, system bus interfacing and other system considerations are also addressed.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122142080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Single-chip RNS two port parallel adaptor for wave digital filters 单片RNS双端口并行适配器，用于波数字滤波器
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212895
G. Cardarilli, F. Sargeni
{"title":"Single-chip RNS two port parallel adaptor for wave digital filters","authors":"G. Cardarilli, F. Sargeni","doi":"10.1109/EUASIC.1991.212895","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212895","url":null,"abstract":"A method based on the residue number system (RNS) arithmetic is used. This method allows one to overcome these difficulties and to obtain high speed and low complexity WDF devices. In particular, the speed performance can be improved through the use of parallel processors defined in terms of RNS, while the occupied area can be reduced realizing suitable isomorphism tables and reducing multiplier complexity to that of a sum. In this paper, an ASIC RNS implementation of a two-port constrained parallel adaptor for WDFs is presented.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116585311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Algebraic decomposition of MCNC benchmark FSMs for logic synthesis 用于逻辑综合的MCNC基准fsm代数分解
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212876
T. Muller-Wipperfurth, M. Geiger
{"title":"Algebraic decomposition of MCNC benchmark FSMs for logic synthesis","authors":"T. Muller-Wipperfurth, M. Geiger","doi":"10.1109/EUASIC.1991.212876","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212876","url":null,"abstract":"An interactive application of algebraic structure theory is presented to decompose finite state machines (FSMs) for logic synthesis purposes. Parallel and serial decompositions with symbolic states are achieved. CASTOR, JEDI ESPRESSO, and MIS are utilized to perform state assignment and logic minimization. Experimental results of two-level and multi-level implementations of MCNC benchmark FSMs are presented.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114347498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Serial data interface for telecommunication satellites 通信卫星串行数据接口
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212859
J. Vanneuville, H. Manhaeve, D. Gevaert
{"title":"Serial data interface for telecommunication satellites","authors":"J. Vanneuville, H. Manhaeve, D. Gevaert","doi":"10.1109/EUASIC.1991.212859","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212859","url":null,"abstract":"The transmitters and receivers to be installed in the satellites of the European data relay system are adjusted by means of a serial data interface. The adjustment consists of a telecommand function and a telemetry function. The serial data interface has been designed, processed and tested. The design was done by using Silvar Lisco software with the 3 mu m CMOS standard-cell library of Mietec.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131620671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fast data path multiplier 快速数据路径乘法器
Euro ASIC '91 Pub Date : 1991-05-27 DOI: 10.1109/EUASIC.1991.212855
C. Priol, P. Magarshack
{"title":"A fast data path multiplier","authors":"C. Priol, P. Magarshack","doi":"10.1109/EUASIC.1991.212855","DOIUrl":"https://doi.org/10.1109/EUASIC.1991.212855","url":null,"abstract":"The authors describe a highly configurable, compiled, fast data path multiplier implemented in the CSAM ASIC technology-independent library based on the GDT/GENESIL silicon compiler environments. The multiplier compiler, which allows independent control of the width of both operands, has been designed for use in high performance applications in data processing with a one stage pipeline option. The authors present the hardware organization combining the modified Booth decoding method and a tree algorithm to reduce the multiplication delay. It is the first time such a tree algorithm compiler is reported for the data path.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128793290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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