用于图像膨胀和侵蚀的ASIC

Euro ASIC '91 Pub Date : 1991-05-27 DOI:10.1109/EUASIC.1991.212857

M. Baatour, J. Rampon, Y. Tertre

{"title":"用于图像膨胀和侵蚀的ASIC","authors":"M. Baatour, J. Rampon, Y. Tertre","doi":"10.1109/EUASIC.1991.212857","DOIUrl":null,"url":null,"abstract":"A VLSI chip to compute two morphological operations, dilation and erosion, over discrete black and white images is presented here. The chip contains 96 PEs organized as a 12*8 2D array of processing elements (PEs) performing in an SIMD mode. Each PE is connected to its four neighbors.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An ASIC for image dilation and erosion\",\"authors\":\"M. Baatour, J. Rampon, Y. Tertre\",\"doi\":\"10.1109/EUASIC.1991.212857\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A VLSI chip to compute two morphological operations, dilation and erosion, over discrete black and white images is presented here. The chip contains 96 PEs organized as a 12*8 2D array of processing elements (PEs) performing in an SIMD mode. Each PE is connected to its four neighbors.<<ETX>>\",\"PeriodicalId\":118990,\"journal\":{\"name\":\"Euro ASIC '91\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Euro ASIC '91\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUASIC.1991.212857\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Euro ASIC '91","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUASIC.1991.212857","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

一种VLSI芯片计算两种形态操作，膨胀和侵蚀，在这里提出了离散的黑白图像。该芯片包含96个pe，组织为一个12*8的二维处理元素阵列(pe)，以SIMD模式执行。每台PE都与它的四个邻居相连。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An ASIC for image dilation and erosion

A VLSI chip to compute two morphological operations, dilation and erosion, over discrete black and white images is presented here. The chip contains 96 PEs organized as a 12*8 2D array of processing elements (PEs) performing in an SIMD mode. Each PE is connected to its four neighbors.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Euro ASIC '91

自引率

0.00%

发文量