{"title":"快速测试asic","authors":"C. Gauthron","doi":"10.1109/EUASIC.1991.212843","DOIUrl":null,"url":null,"abstract":"At-speed test of ASICs is effective to detect delay faults, however, strobing is difficult because of process variations. In this paper two methodologies to generate at-speed test vectors are described. One is based on the comparison and merger of simulation traces obtained with different timing conditions. The other is a two-pass test approach.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"109 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Testing ASICs at-speed\",\"authors\":\"C. Gauthron\",\"doi\":\"10.1109/EUASIC.1991.212843\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"At-speed test of ASICs is effective to detect delay faults, however, strobing is difficult because of process variations. In this paper two methodologies to generate at-speed test vectors are described. One is based on the comparison and merger of simulation traces obtained with different timing conditions. The other is a two-pass test approach.<<ETX>>\",\"PeriodicalId\":118990,\"journal\":{\"name\":\"Euro ASIC '91\",\"volume\":\"109 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Euro ASIC '91\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUASIC.1991.212843\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Euro ASIC '91","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUASIC.1991.212843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
At-speed test of ASICs is effective to detect delay faults, however, strobing is difficult because of process variations. In this paper two methodologies to generate at-speed test vectors are described. One is based on the comparison and merger of simulation traces obtained with different timing conditions. The other is a two-pass test approach.<>
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