{"title":"A dedicated circuit for real time motion estimation","authors":"O. Colavin, A. Artieri, J. Naviner, R. Pacalet","doi":"10.1109/EUASIC.1991.212886","DOIUrl":null,"url":null,"abstract":"Presents a circuit dedicated to real-time motion estimation in video compression systems. It computes motion vectors in the range -8/+7 for 8*4n and 16*4n sized blocks at pixel rates up to 18 MHz. The architecture is based on a 128 processor systolic array. This 270000 transistor IC uses a two metal layer 1.2 mu m CMOS process.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Euro ASIC '91","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUASIC.1991.212886","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
Presents a circuit dedicated to real-time motion estimation in video compression systems. It computes motion vectors in the range -8/+7 for 8*4n and 16*4n sized blocks at pixel rates up to 18 MHz. The architecture is based on a 128 processor systolic array. This 270000 transistor IC uses a two metal layer 1.2 mu m CMOS process.<>