A data-flow processor for real-time low-level image processing

A chip featuring two coupled data-flow processors (DFPs) has been designed. It is to be mesh-connected into large processor arrays dedicated primarily to image processing. Each processor operates on 25 MBytes/s data-flows and performs up to 50 million 8- or 16-bit arithmetic operations per second. The chip has been processed in a 1 mu m CMOS technology. It includes 160000 transistors in a 84 mm/sup 2/ die size area, its clock is at 25 MHz and it is packaged in a 144-pin PGA package. Computations are performed on the fly on a data-flow that comes from a digital video camera. One physical operator is associated to each operation involved in the algorithm. An experimental data-flow system including eight processors in a 2*2*2 3D network has been built. Edge detection, row sums, column sums and histograms have been implemented on it at digital video speed.<>