M. Morante, L. Saiz de Quevedo, P. Tabuenca, J.I. Martinez, E. Villar
{"title":"实现了一个线性数组元素的矩阵乘法","authors":"M. Morante, L. Saiz de Quevedo, P. Tabuenca, J.I. Martinez, E. Villar","doi":"10.1109/EUASIC.1991.212861","DOIUrl":null,"url":null,"abstract":"The implementation of a linear array element for matrix multiplication is described. The cell corresponds to the fully pipelined model. First, its architecture and floorplan are described. Secondly, the design process is completed. Third, its area and time performances are analyzed and finally, the testing of the chips is carried out.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"130 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Implementation of a linear array element for matrix multiplication\",\"authors\":\"M. Morante, L. Saiz de Quevedo, P. Tabuenca, J.I. Martinez, E. Villar\",\"doi\":\"10.1109/EUASIC.1991.212861\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The implementation of a linear array element for matrix multiplication is described. The cell corresponds to the fully pipelined model. First, its architecture and floorplan are described. Secondly, the design process is completed. Third, its area and time performances are analyzed and finally, the testing of the chips is carried out.<<ETX>>\",\"PeriodicalId\":118990,\"journal\":{\"name\":\"Euro ASIC '91\",\"volume\":\"130 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Euro ASIC '91\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUASIC.1991.212861\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Euro ASIC '91","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUASIC.1991.212861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of a linear array element for matrix multiplication
The implementation of a linear array element for matrix multiplication is described. The cell corresponds to the fully pipelined model. First, its architecture and floorplan are described. Secondly, the design process is completed. Third, its area and time performances are analyzed and finally, the testing of the chips is carried out.<>