High speed CMOS operational amplifier

Abstract

In this paper authors present a new approach to fast CMOS opamp design. This approach benefits from the advantages offered by full complementary implementations of well known subcircuits, to enhance the speed of such an operational amplifier and to better organize and economize layout generation. Since the consequent structured topology of full complementary circuits like the present opamp is well suited to a cell based design, simulation time and layout generation time could have been decreased by a factor of almost five. This results in an opamp which exhibits a slew-rate of 800 V/ mu s (for a positive input step) and whose mask layout was done in three days.<>