ASIC chip set development for PCM 2 and 3-ary group MUX and DEMUX with EIS project

Abstract

The author describes a two ASICs design of a PCM 2 and 3-ary group multiplexer and demultiplexer based on the VENUS-S system. The ASIC chip set meets the requirements of multiplex equipment and is in accord with CCITT recommendations. A positive justification circuit had been adopted. HDB3 encoder/decoder and system fault alarm circuit are internal. Measurement of the system shows that the performance of the equipment which uses a MUX/DEMUX ASIC is better than the old one. Its power consumption is less than 14 W for 3-ary and 3.5 W for 2-ary.<>