Integrating verification testing and logic synthesis

Abstract

In this paper, a new design strategy, in which built-in self test (BIST) synthesis tightly interacts with the functional logic design, is described. The authors' method is aimed at VLSI combinational circuits. The BIST design procedure is based on the concept of verification testing. Compared to circuits obtained using conventional design methods, they obtain a reduction in the test signals required and, as a consequence, a substantial reduction in test length and in the complexity of the built-in test pattern generator.<>