Comprehensive CAD support for boundary scan implementation in ASICs

Abstract

The authors review the complete automated implementation of the IEEE P1149.1 boundary scan standard proposed in the CSAM ASIC compiled technology-independent library based on the GDT/GENESIL silicon compiler environments. The advantage of this compiled approach is to provide a flexible set of boundary scan cells, including pads and test access port (TAP) controllers. The boundary scan register is automatically created when compiling the pad ring and different parameterized function complexities allow easily the dedication of the TAP controller to any application. The user-defined elements implementation is also supported, especially by means of logic synthesis, and a test vector generation tool allows one to automatically generate the serial boundary scan test vectors from the parallel test vectors defined for the manufacturing test of the circuit. The cost of boundary scan integration has shown to be reasonable in the manufactured chips.<>