Timing driven pin assignment in a hierarchical design environment

Abstract

Presents a method for taking into account timing constraints during pin assignment, a subtask of floorplanning. Previous approaches to the pin assignment problem determine pin positions or admissible intervals on the block perimeters with the lengths of the respective nets as the only objective. Th authors describe a delay model for hierarchical combinational circuits which defines a linkage between the pins of different global nets in terms of timing dependencies. Based on this model they propose a slack optimization algorithm, which optimizes pin positions and routes for the global nets with respect to the timing requirements.<>