{"title":"基于亚微米asic的处理器芯片设计","authors":"H. Schettler","doi":"10.1109/EUASIC.1991.212893","DOIUrl":null,"url":null,"abstract":"The processor chip set of the Low End ES/9000 is implemented on five CMOS VLSI Chips containing 2.8 Million transistors with an effective channel length of 0.5 mu m. The chips are packaged on multi-chip and single-chip modules. The worst case operating frequency is 35 MHz. The experience gained during the design of this processor is used to extrapolate into submicron technology down to 0.25 mu m. The result is the expectation of a tremendous density and performance increase within the next decade.<<ETX>>","PeriodicalId":118990,"journal":{"name":"Euro ASIC '91","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Processor chip design on submicron ASICs\",\"authors\":\"H. Schettler\",\"doi\":\"10.1109/EUASIC.1991.212893\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The processor chip set of the Low End ES/9000 is implemented on five CMOS VLSI Chips containing 2.8 Million transistors with an effective channel length of 0.5 mu m. The chips are packaged on multi-chip and single-chip modules. The worst case operating frequency is 35 MHz. The experience gained during the design of this processor is used to extrapolate into submicron technology down to 0.25 mu m. The result is the expectation of a tremendous density and performance increase within the next decade.<<ETX>>\",\"PeriodicalId\":118990,\"journal\":{\"name\":\"Euro ASIC '91\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Euro ASIC '91\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUASIC.1991.212893\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Euro ASIC '91","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUASIC.1991.212893","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
摘要
Low End ES/9000的处理器芯片组是在5个包含280万个晶体管的CMOS VLSI芯片上实现的，有效通道长度为0.5 μ m，这些芯片被封装在多芯片和单芯片模块上。最坏情况下工作频率为35mhz。在该处理器的设计过程中获得的经验被用来推断到亚微米技术，低至0.25 μ m，其结果是预期在未来十年内密度和性能将有巨大的提高
The processor chip set of the Low End ES/9000 is implemented on five CMOS VLSI Chips containing 2.8 Million transistors with an effective channel length of 0.5 mu m. The chips are packaged on multi-chip and single-chip modules. The worst case operating frequency is 35 MHz. The experience gained during the design of this processor is used to extrapolate into submicron technology down to 0.25 mu m. The result is the expectation of a tremendous density and performance increase within the next decade.<>
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