2013 18th IEEE European Test Symposium (ETS)最新文献_第3页

Utilizing circuit structure for scan chain diagnosis 利用电路结构进行扫描链诊断

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569355

Wei-Hen Lo, A. Hsieh, C. Lan, Min-Hsien Lin, TingTing Hwang

引用次数: 8

BIST architecture to detect defects in tsvs during pre-bond testing BIST体系结构，用于在粘接前测试中检测tsvs中的缺陷

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569389

D. Arumí, R. Rodríguez-Montañés, J. Figueras

引用次数: 5

RF BIST and test strategy for the receive part of an RF transceiver in CMOS technology 基于CMOS技术的射频收发器接收部分的测试策略

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569387

C. Kelma, S. Darfeuille, A. Neuburger, Andreas Lobnig

引用次数: 1

New test compression scheme based on low power BIST 基于低功耗BIST的测试压缩新方案

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569374

J. Tyszer, M. Filipek, Grzegorz Mrugalski, N. Mukherjee, J. Rajski

引用次数: 7

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability 工艺变异性影响下SRAM芯单元的阻性开口缺陷分析

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569373

E. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine

{"title":"Analyzing resistive-open defects in SRAM core-cell under the effect of process variability","authors":"E. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine","doi":"10.1109/ETS.2013.6569373","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569373","url":null,"abstract":"Functional operations of a Static Random Access Memory (SRAM) are strongly affected by random variability in core-cell transistors and by the variability-induced threshold voltage mismatch between the transistors of the Input-Output (IO) circuitry (especially Sense Amplifiers). This variability also affects the faulty behavior of the SRAM array. This paper is focused on the analysis of static and dynamic faults due to resistive-open defects in the SRAM core-cell, taking into account the effects of random process variability in core-cells and IO circuitry. Statistical analyses have been performed to evaluate the SRAM failure probabilities accounting for defects at each possible location. The results show that random process variability in the SRAM core-cell and IO circuitry have an important effect on the behavior of an SRAM array and also on the defect coverage of various commonly-used test sequences. It is shown that under variability, the minimum defect size detected with maximum probability is more than 2X larger than the minimum size detected in nominal conditions, thus leaving a large range of defects undetected. Several stress conditions during test have been evaluated to assess their capability to increase the defect coverage under random process variability.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125351760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Run-time detection of hardware Trojans: The processor protection unit 硬件木马运行时检测:处理器保护单元

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569378

Jeremy Dubeuf, D. Hély, R. Karri

引用次数: 39

Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes? 在未来的技术节点中，电子行业正在做什么来赢得与预期的可怕故障率的战斗?

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569360

S. Hamdioui, D. Appello, Arnaud Grasset, Xinli Gu, B. Kruseman, R. Mariani, H. Obermeir, S. Venkataraman

{"title":"Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?","authors":"S. Hamdioui, D. Appello, Arnaud Grasset, Xinli Gu, B. Kruseman, R. Mariani, H. Obermeir, S. Venkataraman","doi":"10.1109/ETS.2013.6569360","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569360","url":null,"abstract":"The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10−2 for SRAM and of 10−3 for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications. The panel session aims at gathering opinions from electronics industry on the above challenges and discuss some strategic approaches to provide resilience against intrinsic, random and extrinsic failures. Some questions we hope to be answered are: • Is the electronics industry already facing any reliability issues? How big is the problem? • What is the industry using today to realize reliable and robust systems? Is this going to changes soon? • Can reliability problems prevent using smaller technology nodes in run-time and safety critical applications? • How is reliability evaluation done today? Are there any tools? • Are reliability problems going to become server with technology scaling? Can we quantify? • What is industry doing to prepare themselves and prevent the scary expected failure rates? • Do they need a deep understanding of the technology in order to provide efficient solutions? • What is the best approach to use (bottom-up or top-down)? • Etc.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131912046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Scan pattern retargeting and merging with reduced access time 扫描模式重定位和合并与减少访问时间

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569354

R. Baranowski, M. Kochte, H. Wunderlich

{"title":"Scan pattern retargeting and merging with reduced access time","authors":"R. Baranowski, M. Kochte, H. Wunderlich","doi":"10.1109/ETS.2013.6569354","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569354","url":null,"abstract":"Efficient access to on-chip instrumentation is a key enabler for post-silicon validation, debug, bringup or diagnosis. Reconfigurable scan networks, as proposed by e.g. the IEEE Std. P1687, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. To access an element in a reconfigurable scan network, a scan-in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the scan pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This work presents a method for scan pattern generation with reduced access time. We map the access time reduction to a pseudo-Boolean optimization problem, which enables the use of efficient solvers to exhaustively explore the search space of valid scan-in sequences. This is the first automated method for efficient pattern retargeting in complex reconfigurable scan architectures such as P1687-based networks. It supports the concurrent access to multiple target scan registers (access merging) and generates reduced (short) scan-in sequences, considering all sequential and combinational dependencies. The proposed method achieves an access time reduction by up to 88× or 2.4× in average w.r.t. unoptimized satisfying solutions.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128335727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

Robust optimization of test-architecture designs for core-based SoCs 基于核心的soc测试架构设计的稳健优化

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569348

Sergej Deutsch, K. Chakrabarty

{"title":"Robust optimization of test-architecture designs for core-based SoCs","authors":"Sergej Deutsch, K. Chakrabarty","doi":"10.1109/ETS.2013.6569348","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569348","url":null,"abstract":"Today's technology allows for the integration of many cores in a single die, for instance, in core-based SoCs, and an even larger number of cores are likely to be integrated over multiple layers in a 3D stack. In order to minimize test cost, the test architecture in a core-based SOC is optimized for minimum test time. Optimization methods in use today assume that all relevant input parameters, such as core test time and power consumption during test, are known at the design stage. However, these parameters can change after manufacturing and, in that scenario, the originally designed test architecture may no longer be optimal. Moreover, conventional optimization methods have to consider worst-case estimates for all input parameters to ensure feasibility, which can result in conservative and hence expensive solutions. We propose the use of robust optimization for test-architecture design and test scheduling. This goal of this approach is to find a solution that remains close to optimal in the presence of parameter variations. Experimental results for the ITC'02 SoC benchmarks show that, compared to optimization methods that target only a single point in the input-parameter space, robust optimization can better optimize test time in the presence of parameter variations.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128540121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Generation of compact multi-cycle diagnostic test sets 生成紧凑型多周期诊断测试仪

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569382

I. Pomeranz

引用次数: 3