2013 18th IEEE European Test Symposium (ETS)最新文献

{"title":"Utilizing circuit structure for scan chain diagnosis","authors":"Wei-Hen Lo, A. Hsieh, C. Lan, Min-Hsien Lin, TingTing Hwang","doi":"10.1109/ETS.2013.6569355","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569355","url":null,"abstract":"Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper, we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip flops. After partition step, the ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC'99 benchmarks.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"521 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122224588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BIST architecture to detect defects in tsvs during pre-bond testing","authors":"D. Arumí, R. Rodríguez-Montañés, J. Figueras","doi":"10.1109/ETS.2013.6569389","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569389","url":null,"abstract":"Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123935741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New test compression scheme based on low power BIST","authors":"J. Tyszer, M. Filipek, Grzegorz Mrugalski, N. Mukherjee, J. Rajski","doi":"10.1109/ETS.2013.6569374","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569374","url":null,"abstract":"This paper describes a new programmable low power test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the existing logic BIST infrastructure. The proposed hybrid scheme efficiently combines test compression with logic BIST, where both techniques can work synergistically to deliver high quality test. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125049938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analyzing resistive-open defects in SRAM core-cell under the effect of process variability","authors":"E. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine","doi":"10.1109/ETS.2013.6569373","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569373","url":null,"abstract":"Functional operations of a Static Random Access Memory (SRAM) are strongly affected by random variability in core-cell transistors and by the variability-induced threshold voltage mismatch between the transistors of the Input-Output (IO) circuitry (especially Sense Amplifiers). This variability also affects the faulty behavior of the SRAM array. This paper is focused on the analysis of static and dynamic faults due to resistive-open defects in the SRAM core-cell, taking into account the effects of random process variability in core-cells and IO circuitry. Statistical analyses have been performed to evaluate the SRAM failure probabilities accounting for defects at each possible location. The results show that random process variability in the SRAM core-cell and IO circuitry have an important effect on the behavior of an SRAM array and also on the defect coverage of various commonly-used test sequences. It is shown that under variability, the minimum defect size detected with maximum probability is more than 2X larger than the minimum size detected in nominal conditions, thus leaving a large range of defects undetected. Several stress conditions during test have been evaluated to assess their capability to increase the defect coverage under random process variability.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125351760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RF BIST and test strategy for the receive part of an RF transceiver in CMOS technology","authors":"C. Kelma, S. Darfeuille, A. Neuburger, Andreas Lobnig","doi":"10.1109/ETS.2013.6569387","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569387","url":null,"abstract":"This paper focuses on the RF BIST architecture of the receive path of an RF transceiver processed in the NXP in house CMOS technology with 0.14μm gate length.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Run-time detection of hardware Trojans: The processor protection unit","authors":"Jeremy Dubeuf, D. Hély, R. Karri","doi":"10.1109/ETS.2013.6569378","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569378","url":null,"abstract":"Typical SOC designs use processors and therefore, trust in such processor cores is essential. The 2011 Embedded Systems Challenge (ESC 2011) [1] showed a wide range of possibilities to attack a processor through hardware Trojans. We propose an approach to detect suspicious behavior of a processor and thus assess if the processor is trustworthy or not. A countermeasure, called Processor Protection Unit (PPU) is presented focusing on its design to be particularly resilient against hardware Trojan insertion.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129623576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?","authors":"S. Hamdioui, D. Appello, Arnaud Grasset, Xinli Gu, B. Kruseman, R. Mariani, H. Obermeir, S. Venkataraman","doi":"10.1109/ETS.2013.6569360","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569360","url":null,"abstract":"The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10−2 for SRAM and of 10−3 for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications. The panel session aims at gathering opinions from electronics industry on the above challenges and discuss some strategic approaches to provide resilience against intrinsic, random and extrinsic failures. Some questions we hope to be answered are: • Is the electronics industry already facing any reliability issues? How big is the problem? • What is the industry using today to realize reliable and robust systems? Is this going to changes soon? • Can reliability problems prevent using smaller technology nodes in run-time and safety critical applications? • How is reliability evaluation done today? Are there any tools? • Are reliability problems going to become server with technology scaling? Can we quantify? • What is industry doing to prepare themselves and prevent the scary expected failure rates? • Do they need a deep understanding of the technology in order to provide efficient solutions? • What is the best approach to use (bottom-up or top-down)? • Etc.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131912046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient system-level testing and adaptive tuning of MIMO-OFDM wireless transmitters","authors":"S. Devarakond, D. Banerjee, A. Banerjee, Shreyas Sen, A. Chatterjee","doi":"10.1109/ETS.2013.6569363","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569363","url":null,"abstract":"A low cost methodology for simultaneous testing and tuning of multiple chains of MIMO-OFDM wireless transmitter for system-level specifications is presented. Bandwidth-partitioned test stimuli enable the determination of the behavioral characteristics of the different chains of the RF transmitter using a one-time data acquisition. The determined behavioral characteristics of the transmitters are then correlated to system-level specifications in the simulation environment. Using the test setup, a power conscious system-level tuning approach for yield improvement is developed for tuning of parametric deviations. A yield improvement of 20% is obtained using the proposed methodology. Finally, an adaptive tuning approach is presented for those devices that face increased reliability risks/power-budget violations due to the excessive power consumption caused by post-manufacturing tuning. The tuning methodology achieves new performance metrics for these devices that attempt to maximize the conditions under which the device operates. Significant improvement in yield is obtained using the adaptive tuning methodology. Preliminary hardware validation of the proposed methodology using off the shelf components is performed.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121090645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Current testing: Dead or alive?","authors":"H. Manhaeve, P. Harrod, A. Singh, C. Patel, Ralf Arnolc, D. Appello","doi":"10.1109/ETS.2013.6569367","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569367","url":null,"abstract":"Summary form only given. Current, voltage and time (frequency) are the base parameters describing an electronic system. In the 1700's, Benjamin Franklin was one of the first experimenting with current tests, followed by many others shaping the current domain. In 1963 Frank Wanlass (Fairchild Semiconductor) planted the first seeds of using current testing as part of a structural approach to validate integrated circuits when publishing the concept of complementary-MOS (CMOS) logic circuitry. It occurred to him that a CMOS circuit would use very little power and that in standby; it would draw practically nothing - just the leakage current. It was therefore a fact that CMOS circuits with increased standby power consumption were defective. In 1981 Mark W. Levi demonstrated the concept of IDDQ testing (validating circuits by measuring and observing their quiescent supply current) in his ITC'1981 paper “CMOS is most Testable”. This paper kicked off a lot of research on IDDQ fault modeling, IDDQ defect detection capabilities, IDDQ and reliability, IDDQ efficiency. Much of that research happened in the late eighties - early nineties by “Chuck and Jerry”, exploring the benefits, followed by studies done by HP, IBM, TI, Philips, Alcatel, Ford Micro, ... Since then IDDQ testing became synonym to current testing. Extensive research revealed the IDDQ capabilities. Despite its demonstrated defect detection capabilities and screening efficiency, it was not an easy way for IDDQ to make it to the production test floor. The initial lack of commercial available ATPG tools and suitable measurement solutions were the hurdles to take. Then in 1996 a paper on \" IDDQ test: sensitivity analysis of scaling\" was published at ITC by Tom Williams at al. The purpose of this paper was to issue a warning that more complex IDDQ test schemes might be needed in future to deal with increased device complexity and increased background leakage, however it was interpreted as predicting the end of current testing (single threshold IDDQ more in particular) at least for high performance ICs. Next to current testing being a synonym for IDDQ testing, there is a wide variety of test processes out there where current measurements make up an important part of the test. The panel will revisit the ITC'96 prediction, make up a status and address questions such as: Is IDDQ testing (and its derivative such as delta IDDQ, current ratios, etc.) still applied these days and if so for which types of ICs and for what purposes (only leakage current measurements, test and diagnosis of bridging defects, etc.)?. IDDQ testing (and its derivative) is the dominant form of current testing. What about the others?. Does the actual use of current testing require/motivate/justify research on that topic?. Are the obstacles which led to the removal of current testing from test suites really impossible to overcome? What are these obstacles? Have we tried everything?. What other forms of current testing/current measure","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115204361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scan pattern retargeting and merging with reduced access time","authors":"R. Baranowski, M. Kochte, H. Wunderlich","doi":"10.1109/ETS.2013.6569354","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569354","url":null,"abstract":"Efficient access to on-chip instrumentation is a key enabler for post-silicon validation, debug, bringup or diagnosis. Reconfigurable scan networks, as proposed by e.g. the IEEE Std. P1687, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. To access an element in a reconfigurable scan network, a scan-in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the scan pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This work presents a method for scan pattern generation with reduced access time. We map the access time reduction to a pseudo-Boolean optimization problem, which enables the use of efficient solvers to exhaustively explore the search space of valid scan-in sequences. This is the first automated method for efficient pattern retargeting in complex reconfigurable scan architectures such as P1687-based networks. It supports the concurrent access to multiple target scan registers (access merging) and generates reduced (short) scan-in sequences, considering all sequential and combinational dependencies. The proposed method achieves an access time reduction by up to 88× or 2.4× in average w.r.t. unoptimized satisfying solutions.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128335727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}