2013 18th IEEE European Test Symposium (ETS)最新文献_第4页

A mutual characterization based SAR ADC self-testing technique 一种基于互表征的SAR ADC自测试技术

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569365

H.-J. Lin, X.-L. Huang, J.-L. Huang

引用次数: 6

Robust optimization of test-architecture designs for core-based SoCs 基于核心的soc测试架构设计的稳健优化

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569348

Sergej Deutsch, K. Chakrabarty

{"title":"Robust optimization of test-architecture designs for core-based SoCs","authors":"Sergej Deutsch, K. Chakrabarty","doi":"10.1109/ETS.2013.6569348","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569348","url":null,"abstract":"Today's technology allows for the integration of many cores in a single die, for instance, in core-based SoCs, and an even larger number of cores are likely to be integrated over multiple layers in a 3D stack. In order to minimize test cost, the test architecture in a core-based SOC is optimized for minimum test time. Optimization methods in use today assume that all relevant input parameters, such as core test time and power consumption during test, are known at the design stage. However, these parameters can change after manufacturing and, in that scenario, the originally designed test architecture may no longer be optimal. Moreover, conventional optimization methods have to consider worst-case estimates for all input parameters to ensure feasibility, which can result in conservative and hence expensive solutions. We propose the use of robust optimization for test-architecture design and test scheduling. This goal of this approach is to find a solution that remains close to optimal in the presence of parameter variations. Experimental results for the ITC'02 SoC benchmarks show that, compared to optimization methods that target only a single point in the input-parameter space, robust optimization can better optimize test time in the presence of parameter variations.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128540121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Generation of compact multi-cycle diagnostic test sets 生成紧凑型多周期诊断测试仪

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569382

I. Pomeranz

引用次数: 3

Outlook for many-core systems: Cloudy with a chance of virtualization 多核系统的前景:多云，有虚拟化的机会

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569347

N. Dutt

{"title":"Outlook for many-core systems: Cloudy with a chance of virtualization","authors":"N. Dutt","doi":"10.1109/ETS.2013.6569347","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569347","url":null,"abstract":"The emergence of many-core platforms increases the need for high memory bandwidth, which in turn creates the need for vast amounts of on-chip memory space. Designers must carefully provision the on-chip memory resources to meet application needs. Efficient memory management is extremely critical since it has a great impact on the system's power consumption and throughput. While memory hierarchies have traditionally been based on SRAM-based on-chip caches, the demands of predictability, low power/energy, as well as the emergence of non-volatile memories (NVMs) and mixed-criticality systems, have led to increasing use of software-controlled on-chip memories. The talk presents strategies for efficiently managing software-controlled memories in the many-core domain, while addressing the disparate challenges faced by designers in deploying such memory subsystems (e.g., sharing memory resources, handling variability, and deploying heterogeneous memory families). The overall approach revisits and extends the classical notion of clouds and memory virtualization to handle scalable on-chip memory organizations for reduced power consumption, security, reliability and yield management.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133113230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Magical thinking applied to test engineering reality (and vice versa) 将神奇的思维应用于测试工程现实(反之亦然)

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569346

J. Rearick

引用次数: 0

Efficient minimization of test frequencies for linear analog circuits 线性模拟电路测试频率的有效最小化

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569385

Mohand Bentobache, A. Bounceur, R. Euler, Yann Kieffer, S. Mir

引用次数: 3

Optimization for timing-speculated circuits by redundancy addition and removal 基于冗余添加和去除的时序推测电路优化

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569376

Yuxi Liu, Rong Ye, F. Yuan, Q. Xu

引用次数: 1

Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis 指导板级故障诊断的信息论综合症和根本原因分析

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569364

Fangming Ye, Zhaobo Zhang, K. Chakrabarty, Xinli Gu

{"title":"Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis","authors":"Fangming Ye, Zhaobo Zhang, K. Chakrabarty, Xinli Gu","doi":"10.1109/ETS.2013.6569364","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569364","url":null,"abstract":"High-volume manufacturing of complex electronic products involves functional test at board level to ensure low defect escapes. Machine-learning techniques have recently been proposed for reasoning-based functional-fault diagnosis system to achieve high diagnosis accuracy. However, machine learning requires a rich set of test items (syndromes) and a sizable database of faulty boards. An insufficient number of failed boards, ambiguous root-cause identification, and redundant or irrelevant syndromes can render machine learning ineffective. We propose an evaluation and enhancement framework based on information theory for guiding diagnosis systems using syndrome and root-cause analysis. Syndrome analysis based on subset selection provides a representative set of syndromes with minimum redundancy and maximum relevance. Root-cause analysis measures the discriminative ability of differentiating a given root cause from others. The metrics obtained from the proposed framework can also provide guidelines for test redesign to enhance diagnosis. A real board from industry, currently in volume production, and an additional synthetic board, based on data extrapolated from another real board, are used to demonstrate the effectiveness of the proposed framework.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134338566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Novel approach to reduce power droop during scan-based logic BIST 一种降低基于扫描的逻辑BIST功率下降的新方法

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569375

M. Omaña, Daniele Rossi, Filippo Fuzzi, C. Metra, C. Tirumurti, R. Galivache

引用次数: 13

Semiconductor failure modes and mitigation for critical systems embedded tutorial 嵌入式关键系统的半导体故障模式及缓解

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569369

H. Manhaeve, E. Mikkola

{"title":"Semiconductor failure modes and mitigation for critical systems embedded tutorial","authors":"H. Manhaeve, E. Mikkola","doi":"10.1109/ETS.2013.6569369","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569369","url":null,"abstract":"The mounting issues of decreased yield and reliability from nanoscale integrated circuit (IC) processes require advanced approaches to the measurement and mitigation of device degradation and variance. Shrinking process geometries, with their corresponding reduction in device lifetimes, have broad implications to critical applications having long intended design lifetimes and are a major concern to the long-term reliability of safety-critical systems in aerospace and automotive applications. Common semiconductor failure modes include, among others, time-dependent dielectric breakdown (TDDB), hot carrier injection (BCI) damage, and negative bias temperature instability (NBTI). Die-level prognostic test structures can detect and help mitigate untimely failures in critical systems. These test structures, with variance measurement capabilities, also provide an effective platform for improved process-aware design for improved yields. This tutorial addresses concepts of in-situ test structures as a solution to product yield enhancement, process reliability qualification and reliability monitoring throughout the lifetime of the product and include practical application examples.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129726376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1