2013 18th IEEE European Test Symposium (ETS)最新文献_第4页

A mutual characterization based SAR ADC self-testing technique 一种基于互表征的SAR ADC自测试技术

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569365

H.-J. Lin, X.-L. Huang, J.-L. Huang

引用次数: 6

Scan pattern retargeting and merging with reduced access time 扫描模式重定位和合并与减少访问时间

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569354

R. Baranowski, M. Kochte, H. Wunderlich

{"title":"Scan pattern retargeting and merging with reduced access time","authors":"R. Baranowski, M. Kochte, H. Wunderlich","doi":"10.1109/ETS.2013.6569354","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569354","url":null,"abstract":"Efficient access to on-chip instrumentation is a key enabler for post-silicon validation, debug, bringup or diagnosis. Reconfigurable scan networks, as proposed by e.g. the IEEE Std. P1687, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. To access an element in a reconfigurable scan network, a scan-in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the scan pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This work presents a method for scan pattern generation with reduced access time. We map the access time reduction to a pseudo-Boolean optimization problem, which enables the use of efficient solvers to exhaustively explore the search space of valid scan-in sequences. This is the first automated method for efficient pattern retargeting in complex reconfigurable scan architectures such as P1687-based networks. It supports the concurrent access to multiple target scan registers (access merging) and generates reduced (short) scan-in sequences, considering all sequential and combinational dependencies. The proposed method achieves an access time reduction by up to 88× or 2.4× in average w.r.t. unoptimized satisfying solutions.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128335727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

Outlook for many-core systems: Cloudy with a chance of virtualization 多核系统的前景:多云，有虚拟化的机会

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569347

N. Dutt

{"title":"Outlook for many-core systems: Cloudy with a chance of virtualization","authors":"N. Dutt","doi":"10.1109/ETS.2013.6569347","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569347","url":null,"abstract":"The emergence of many-core platforms increases the need for high memory bandwidth, which in turn creates the need for vast amounts of on-chip memory space. Designers must carefully provision the on-chip memory resources to meet application needs. Efficient memory management is extremely critical since it has a great impact on the system's power consumption and throughput. While memory hierarchies have traditionally been based on SRAM-based on-chip caches, the demands of predictability, low power/energy, as well as the emergence of non-volatile memories (NVMs) and mixed-criticality systems, have led to increasing use of software-controlled on-chip memories. The talk presents strategies for efficiently managing software-controlled memories in the many-core domain, while addressing the disparate challenges faced by designers in deploying such memory subsystems (e.g., sharing memory resources, handling variability, and deploying heterogeneous memory families). The overall approach revisits and extends the classical notion of clouds and memory virtualization to handle scalable on-chip memory organizations for reduced power consumption, security, reliability and yield management.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133113230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient system-level testing and adaptive tuning of MIMO-OFDM wireless transmitters MIMO-OFDM无线发射机的高效系统级测试和自适应调谐

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569363

S. Devarakond, D. Banerjee, A. Banerjee, Shreyas Sen, A. Chatterjee

{"title":"Efficient system-level testing and adaptive tuning of MIMO-OFDM wireless transmitters","authors":"S. Devarakond, D. Banerjee, A. Banerjee, Shreyas Sen, A. Chatterjee","doi":"10.1109/ETS.2013.6569363","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569363","url":null,"abstract":"A low cost methodology for simultaneous testing and tuning of multiple chains of MIMO-OFDM wireless transmitter for system-level specifications is presented. Bandwidth-partitioned test stimuli enable the determination of the behavioral characteristics of the different chains of the RF transmitter using a one-time data acquisition. The determined behavioral characteristics of the transmitters are then correlated to system-level specifications in the simulation environment. Using the test setup, a power conscious system-level tuning approach for yield improvement is developed for tuning of parametric deviations. A yield improvement of 20% is obtained using the proposed methodology. Finally, an adaptive tuning approach is presented for those devices that face increased reliability risks/power-budget violations due to the excessive power consumption caused by post-manufacturing tuning. The tuning methodology achieves new performance metrics for these devices that attempt to maximize the conditions under which the device operates. Significant improvement in yield is obtained using the adaptive tuning methodology. Preliminary hardware validation of the proposed methodology using off the shelf components is performed.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121090645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Magical thinking applied to test engineering reality (and vice versa) 将神奇的思维应用于测试工程现实(反之亦然)

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569346

J. Rearick

引用次数: 0

Efficient minimization of test frequencies for linear analog circuits 线性模拟电路测试频率的有效最小化

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569385

Mohand Bentobache, A. Bounceur, R. Euler, Yann Kieffer, S. Mir

引用次数: 3

Optimization for timing-speculated circuits by redundancy addition and removal 基于冗余添加和去除的时序推测电路优化

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569376

Yuxi Liu, Rong Ye, F. Yuan, Q. Xu

引用次数: 1

Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis 指导板级故障诊断的信息论综合症和根本原因分析

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569364

Fangming Ye, Zhaobo Zhang, K. Chakrabarty, Xinli Gu

{"title":"Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis","authors":"Fangming Ye, Zhaobo Zhang, K. Chakrabarty, Xinli Gu","doi":"10.1109/ETS.2013.6569364","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569364","url":null,"abstract":"High-volume manufacturing of complex electronic products involves functional test at board level to ensure low defect escapes. Machine-learning techniques have recently been proposed for reasoning-based functional-fault diagnosis system to achieve high diagnosis accuracy. However, machine learning requires a rich set of test items (syndromes) and a sizable database of faulty boards. An insufficient number of failed boards, ambiguous root-cause identification, and redundant or irrelevant syndromes can render machine learning ineffective. We propose an evaluation and enhancement framework based on information theory for guiding diagnosis systems using syndrome and root-cause analysis. Syndrome analysis based on subset selection provides a representative set of syndromes with minimum redundancy and maximum relevance. Root-cause analysis measures the discriminative ability of differentiating a given root cause from others. The metrics obtained from the proposed framework can also provide guidelines for test redesign to enhance diagnosis. A real board from industry, currently in volume production, and an additional synthetic board, based on data extrapolated from another real board, are used to demonstrate the effectiveness of the proposed framework.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134338566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Novel approach to reduce power droop during scan-based logic BIST 一种降低基于扫描的逻辑BIST功率下降的新方法

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569375

M. Omaña, Daniele Rossi, Filippo Fuzzi, C. Metra, C. Tirumurti, R. Galivache

引用次数: 13

Semiconductor failure modes and mitigation for critical systems embedded tutorial 嵌入式关键系统的半导体故障模式及缓解

2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569369

H. Manhaeve, E. Mikkola

{"title":"Semiconductor failure modes and mitigation for critical systems embedded tutorial","authors":"H. Manhaeve, E. Mikkola","doi":"10.1109/ETS.2013.6569369","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569369","url":null,"abstract":"The mounting issues of decreased yield and reliability from nanoscale integrated circuit (IC) processes require advanced approaches to the measurement and mitigation of device degradation and variance. Shrinking process geometries, with their corresponding reduction in device lifetimes, have broad implications to critical applications having long intended design lifetimes and are a major concern to the long-term reliability of safety-critical systems in aerospace and automotive applications. Common semiconductor failure modes include, among others, time-dependent dielectric breakdown (TDDB), hot carrier injection (BCI) damage, and negative bias temperature instability (NBTI). Die-level prognostic test structures can detect and help mitigate untimely failures in critical systems. These test structures, with variance measurement capabilities, also provide an effective platform for improved process-aware design for improved yields. This tutorial addresses concepts of in-situ test structures as a solution to product yield enhancement, process reliability qualification and reliability monitoring throughout the lifetime of the product and include practical application examples.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129726376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1