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2013 18th IEEE European Test Symposium (ETS)最新文献

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Approximate computing: An emerging paradigm for energy-efficient design 近似计算:节能设计的新兴范例
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569370
Jie Han, M. Orshansky
{"title":"Approximate computing: An emerging paradigm for energy-efficient design","authors":"Jie Han, M. Orshansky","doi":"10.1109/ETS.2013.6569370","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569370","url":null,"abstract":"Approximate computing has recently emerged as a promising approach to energy-efficient design of digital systems. Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality or optimality in the computed result. By relaxing the need for fully precise or completely deterministic operations, approximate computing techniques allow substantially improved energy efficiency. This paper reviews recent progress in the area, including design of approximate arithmetic blocks, pertinent error and quality measures, and algorithm-level techniques for approximate computing.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124847694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 925
Efficient selection of signatures for analog/RF alternate test 有效地选择模拟/射频交替测试的签名
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569362
Manuel J. Barragan Asian, G. Léger
{"title":"Efficient selection of signatures for analog/RF alternate test","authors":"Manuel J. Barragan Asian, G. Léger","doi":"10.1109/ETS.2013.6569362","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569362","url":null,"abstract":"This work proposes a generic methodology for selecting meaningful subsets of indirect measurements (signatures). This allows precise predictions of the DUT performances and/or precise pass/fail classification of the DUT, while minimizing the number of necessary measurements. Two simple figures of merit are provided for ranking sets of signatures a priori, before training any machine learning model. These two figures evaluate the quality of each signature based on its Brownian distance correlation to the target specifications, and on its local distribution in the proximities of the pass/fail decision boundaries. The proposed methodology is illustrated by its direct application to a DC-based alternate test for LNAs.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122141377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Aggresive scan chain masking for improved diagnosis of multiple scan chain failures 主动扫描链屏蔽改进多扫描链故障诊断
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569383
Subhadip Kundu, S. Chattopadhyay, I. Sengupta, R. Kapur
{"title":"Aggresive scan chain masking for improved diagnosis of multiple scan chain failures","authors":"Subhadip Kundu, S. Chattopadhyay, I. Sengupta, R. Kapur","doi":"10.1109/ETS.2013.6569383","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569383","url":null,"abstract":"When multiple chains, mapped to the same compactor output fail, AND-gate masking logic at the compactor side can be used to aid in diagnosis. The basic idea is: if for some pattern, only one faulty chain is observed and all the other faulty chains are masked, then the corresponding compacted response will only be affected by the non-masked faulty chain. Such a test pattern will help to diagnose that chain.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133048870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
M-S test based on specification validation using octrees in the measure space 基于规格验证的M-S测试，在测量空间中使用八叉树
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569359
Álvaro Gómez-Pau, L. Balado, J. Figueras
{"title":"M-S test based on specification validation using octrees in the measure space","authors":"Álvaro Gómez-Pau, L. Balado, J. Figueras","doi":"10.1109/ETS.2013.6569359","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569359","url":null,"abstract":"Testing M-S circuits is a difficult task demanding high amount of resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure metrics. In this work, a testing technique using octrees in the measure space is presented. Octrees have been used in computer graphics with successful results for rendering, image processing and space clustering applications. In this paper are used to encode the test acceptance region with arbitrary precision after an statistical training phase. Such representation allows an efficient way to test a candidate circuit in terms of test application time. The method is applied to test a Biquad filter with encouraging results. Test escapes and test yield loss caused by parametric variations have been estimated.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128557813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Implementing model redundancy in predictive alternate test to improve test confidence 在预测交替测试中实现模型冗余，提高测试置信度
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569386
H. Ayari, F. Azaïs, S. Bernard, M. Comte, V. Kerzérho, O. Potin, M. Renovell
{"title":"Implementing model redundancy in predictive alternate test to improve test confidence","authors":"H. Ayari, F. Azaïs, S. Bernard, M. Comte, V. Kerzérho, O. Potin, M. Renovell","doi":"10.1109/ETS.2013.6569386","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569386","url":null,"abstract":"This work investigates new implementations of the predictive alternate test strategy that exploit model redundancy in order to improve test confidence. The key idea is to build during the training phase, not only one regression model for each specification as in the classical implementation, but several regression models. We explore various options for implementing model redundancy, based on the use of different indirect measurement combinations and/or different partitions of the training set.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reconciling the IC test and security dichotomy 协调IC测试和安全二分法
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569368
O. Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, R. Karri, Yier Jin, K. Huang, Y. Makris
{"title":"Reconciling the IC test and security dichotomy","authors":"O. Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, R. Karri, Yier Jin, K. Huang, Y. Makris","doi":"10.1109/ETS.2013.6569368","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569368","url":null,"abstract":"Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan'ed and counterfeit ICs.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"14 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126872928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Extracting device-parameter variations using a single sensitivity-configurable ring oscillator 使用单个灵敏度可配置的环形振荡器提取设备参数变化
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569366
Yuma Higuchi, Kenichi Shinkai, M. Hashimoto, R. Rao, S. Nassif
{"title":"Extracting device-parameter variations using a single sensitivity-configurable ring oscillator","authors":"Yuma Higuchi, Kenichi Shinkai, M. Hashimoto, R. Rao, S. Nassif","doi":"10.1109/ETS.2013.6569366","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569366","url":null,"abstract":"The RO(Ring-Oscillator)-based sensor is one of easily-implementable variation sensors, but for decomposing the observed variability into multiple unique device-parameter variations, a large number of ROs with different structures and sensitivities to device-parameters is required. This paper proposes a scheme for sensing multiple device-parameter variations with just a single reconfigurable RO. This sensitivity-configurable RO has a number of configurations available and this property can be exploited for reducing sensor area while improving estimation accuracy through iterative estimation. To minimize the prospective error, the proposed estimation iterates: (1) selecting the best configuration that minimizes the prospective estimation error around the current estimates; and (2) updating the estimates with the selected configuration. This experiment was carried out assuming a 32-nm predictive technology model. Experimental results show that device-parameter extraction with a single RO is feasible and the error of the extracted parameters is reduced by 35 to 53% with the improved objective function and iterative estimation.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"32 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132767612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Hybrid 3D pre-bonding test framework design 混合三维预粘接试验框架设计
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569388
Unni Chandran, Dan Zhao, Rathish Jayabharathi
{"title":"Hybrid 3D pre-bonding test framework design","authors":"Unni Chandran, Dan Zhao, Rathish Jayabharathi","doi":"10.1109/ETS.2013.6569388","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569388","url":null,"abstract":"We have proposed in this paper a hybrid wireless test framework for pre-bond testing of 3D-SICs. This framework exploits high data rate & low noise near field inductive coupling mechanism for test data transfer. Test stimuli for IP cores and test control for TSV BIST are wirelessly transmitted through the probe card. Test responses from IP cores and TSV BIST are relayed back to the probe card by WiPads. A scheduling heuristic was further proposed for parallel testing of TSVs and IP cores, achieving reasonably close testing times to LB.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125144925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On combining alternate test with spatial correlation modeling in analog/RF ICs 模拟/射频集成电路中交替测试与空间相关建模相结合的研究
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569358
K. Huang, Nathan Kupp, J. Carulli, Y. Makris
{"title":"On combining alternate test with spatial correlation modeling in analog/RF ICs","authors":"K. Huang, Nathan Kupp, J. Carulli, Y. Makris","doi":"10.1109/ETS.2013.6569358","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569358","url":null,"abstract":"Statistical intra-die correlation has been extensively studied as a means for reducing test cost in analog/RF ICs. Generally known as alternate test, this approach seeks to predict the performances of an analog/RF chip based on low-cost measurements on the same chip and statistical models learned from a training set of chips. Recently, an orthogonal direction for leveraging statistical correlation towards reducing test cost of analog/RF ICs has also gained traction. Specifically, inter-die spatial correlation models learned from specification tests on a sparse subset of die on a wafer are used to predict performances on the unobserved die. In this work, we investigate the potential of combining these two statistical approaches, anticipating that the performance prediction accuracy of the joint correlation model will surpass the accuracy of its constituents. Experimental results on industrial semiconductor manufacturing data validate this conjecture and corroborate the utility of the combined performance prediction models.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124774295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers 具有嵌入式核心和多塔的3d - sic的自动DfT插入和测试生成
2013 18th IEEE European Test Symposium (ETS) Pub Date : 2013-05-27 DOI: 10.1109/ETS.2013.6569350
C. Papameletis, B. Keller, V. Chickermane, E. Marinissen, S. Hamdioui
{"title":"Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers","authors":"C. Papameletis, B. Keller, V. Chickermane, E. Marinissen, S. Hamdioui","doi":"10.1109/ETS.2013.6569350","DOIUrl":"https://doi.org/10.1109/ETS.2013.6569350","url":null,"abstract":"Three-dimensional stacked integrated circuits (3D-SICs) implemented with through-silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller, and more energy-efficient chips. As all micro-electronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. Previously, we defined, implemented, and automated a 3D-DfT (Design-for-Test) architecture that provides modular test access for 3D-SICs containing monolithic logic dies in a single-tower stack. However, the logic dies comprising a 3D-SIC typically are complex System-on-Chip (SoC) designs that include embedded intellectual property (IP) cores, wrapped for modular test. Also, multi-tower 3D-SICs have started to emerge. In this paper, our existing 3D-DfT architecture is extended with support for wrapped embedded IP cores and multi-tower stacks and its implementation is automated with industrial electronic design automation (EDA) tools.","PeriodicalId":118063,"journal":{"name":"2013 18th IEEE European Test Symposium (ETS)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129841944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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